67b32fe250
Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-10-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
678 lines
19 KiB
C
678 lines
19 KiB
C
/*
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* QEMU paravirtual RDMA
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*
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* Copyright (C) 2018 Oracle
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* Copyright (C) 2018 Red Hat Inc
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*
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* Authors:
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* Yuval Shaia <yuval.shaia@oracle.com>
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_ids.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/msix.h"
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#include "hw/qdev-core.h"
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#include "hw/qdev-properties.h"
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#include "cpu.h"
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#include "trace.h"
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#include "../rdma_rm.h"
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#include "../rdma_backend.h"
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#include "../rdma_utils.h"
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#include <infiniband/verbs.h>
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#include "pvrdma.h"
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#include "standard-headers/rdma/vmw_pvrdma-abi.h"
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#include "standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h"
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#include "pvrdma_qp_ops.h"
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static Property pvrdma_dev_properties[] = {
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DEFINE_PROP_STRING("backend-dev", PVRDMADev, backend_device_name),
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DEFINE_PROP_UINT8("backend-port", PVRDMADev, backend_port_num, 1),
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DEFINE_PROP_UINT8("backend-gid-idx", PVRDMADev, backend_gid_idx, 0),
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DEFINE_PROP_UINT64("dev-caps-max-mr-size", PVRDMADev, dev_attr.max_mr_size,
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MAX_MR_SIZE),
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DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
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DEFINE_PROP_INT32("dev-caps-max-sge", PVRDMADev, dev_attr.max_sge, MAX_SGE),
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DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
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DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
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DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
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DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
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MAX_QP_RD_ATOM),
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DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
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dev_attr.max_qp_init_rd_atom, MAX_QP_INIT_RD_ATOM),
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DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void free_dev_ring(PCIDevice *pci_dev, PvrdmaRing *ring,
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void *ring_state)
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{
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pvrdma_ring_free(ring);
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rdma_pci_dma_unmap(pci_dev, ring_state, TARGET_PAGE_SIZE);
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}
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static int init_dev_ring(PvrdmaRing *ring, struct pvrdma_ring **ring_state,
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const char *name, PCIDevice *pci_dev,
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dma_addr_t dir_addr, uint32_t num_pages)
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{
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uint64_t *dir, *tbl;
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int rc = 0;
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pr_dbg("Initializing device ring %s\n", name);
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pr_dbg("pdir_dma=0x%llx\n", (long long unsigned int)dir_addr);
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pr_dbg("num_pages=%d\n", num_pages);
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dir = rdma_pci_dma_map(pci_dev, dir_addr, TARGET_PAGE_SIZE);
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if (!dir) {
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pr_err("Failed to map to page directory\n");
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rc = -ENOMEM;
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goto out;
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}
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tbl = rdma_pci_dma_map(pci_dev, dir[0], TARGET_PAGE_SIZE);
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if (!tbl) {
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pr_err("Failed to map to page table\n");
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rc = -ENOMEM;
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goto out_free_dir;
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}
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*ring_state = rdma_pci_dma_map(pci_dev, tbl[0], TARGET_PAGE_SIZE);
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if (!*ring_state) {
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pr_err("Failed to map to ring state\n");
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rc = -ENOMEM;
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goto out_free_tbl;
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}
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/* RX ring is the second */
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(*ring_state)++;
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rc = pvrdma_ring_init(ring, name, pci_dev,
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(struct pvrdma_ring *)*ring_state,
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(num_pages - 1) * TARGET_PAGE_SIZE /
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sizeof(struct pvrdma_cqne),
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sizeof(struct pvrdma_cqne),
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(dma_addr_t *)&tbl[1], (dma_addr_t)num_pages - 1);
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if (rc) {
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pr_err("Failed to initialize ring\n");
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rc = -ENOMEM;
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goto out_free_ring_state;
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}
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goto out_free_tbl;
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out_free_ring_state:
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rdma_pci_dma_unmap(pci_dev, *ring_state, TARGET_PAGE_SIZE);
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out_free_tbl:
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rdma_pci_dma_unmap(pci_dev, tbl, TARGET_PAGE_SIZE);
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out_free_dir:
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rdma_pci_dma_unmap(pci_dev, dir, TARGET_PAGE_SIZE);
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out:
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return rc;
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}
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static void free_dsr(PVRDMADev *dev)
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{
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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if (!dev->dsr_info.dsr) {
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return;
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}
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free_dev_ring(pci_dev, &dev->dsr_info.async,
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dev->dsr_info.async_ring_state);
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free_dev_ring(pci_dev, &dev->dsr_info.cq, dev->dsr_info.cq_ring_state);
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rdma_pci_dma_unmap(pci_dev, dev->dsr_info.req,
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sizeof(union pvrdma_cmd_req));
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rdma_pci_dma_unmap(pci_dev, dev->dsr_info.rsp,
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sizeof(union pvrdma_cmd_resp));
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rdma_pci_dma_unmap(pci_dev, dev->dsr_info.dsr,
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sizeof(struct pvrdma_device_shared_region));
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dev->dsr_info.dsr = NULL;
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}
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static int load_dsr(PVRDMADev *dev)
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{
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int rc = 0;
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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DSRInfo *dsr_info;
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struct pvrdma_device_shared_region *dsr;
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free_dsr(dev);
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/* Map to DSR */
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pr_dbg("dsr_dma=0x%llx\n", (long long unsigned int)dev->dsr_info.dma);
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dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
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sizeof(struct pvrdma_device_shared_region));
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if (!dev->dsr_info.dsr) {
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pr_err("Failed to map to DSR\n");
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rc = -ENOMEM;
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goto out;
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}
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/* Shortcuts */
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dsr_info = &dev->dsr_info;
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dsr = dsr_info->dsr;
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/* Map to command slot */
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pr_dbg("cmd_dma=0x%llx\n", (long long unsigned int)dsr->cmd_slot_dma);
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dsr_info->req = rdma_pci_dma_map(pci_dev, dsr->cmd_slot_dma,
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sizeof(union pvrdma_cmd_req));
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if (!dsr_info->req) {
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pr_err("Failed to map to command slot address\n");
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rc = -ENOMEM;
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goto out_free_dsr;
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}
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/* Map to response slot */
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pr_dbg("rsp_dma=0x%llx\n", (long long unsigned int)dsr->resp_slot_dma);
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dsr_info->rsp = rdma_pci_dma_map(pci_dev, dsr->resp_slot_dma,
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sizeof(union pvrdma_cmd_resp));
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if (!dsr_info->rsp) {
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pr_err("Failed to map to response slot address\n");
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rc = -ENOMEM;
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goto out_free_req;
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}
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/* Map to CQ notification ring */
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rc = init_dev_ring(&dsr_info->cq, &dsr_info->cq_ring_state, "dev_cq",
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pci_dev, dsr->cq_ring_pages.pdir_dma,
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dsr->cq_ring_pages.num_pages);
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if (rc) {
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pr_err("Failed to map to initialize CQ ring\n");
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rc = -ENOMEM;
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goto out_free_rsp;
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}
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/* Map to event notification ring */
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rc = init_dev_ring(&dsr_info->async, &dsr_info->async_ring_state,
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"dev_async", pci_dev, dsr->async_ring_pages.pdir_dma,
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dsr->async_ring_pages.num_pages);
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if (rc) {
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pr_err("Failed to map to initialize event ring\n");
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rc = -ENOMEM;
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goto out_free_rsp;
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}
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goto out;
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out_free_rsp:
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rdma_pci_dma_unmap(pci_dev, dsr_info->rsp, sizeof(union pvrdma_cmd_resp));
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out_free_req:
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rdma_pci_dma_unmap(pci_dev, dsr_info->req, sizeof(union pvrdma_cmd_req));
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out_free_dsr:
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rdma_pci_dma_unmap(pci_dev, dsr_info->dsr,
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sizeof(struct pvrdma_device_shared_region));
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dsr_info->dsr = NULL;
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out:
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return rc;
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}
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static void init_dsr_dev_caps(PVRDMADev *dev)
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{
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struct pvrdma_device_shared_region *dsr;
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if (dev->dsr_info.dsr == NULL) {
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pr_err("Can't initialized DSR\n");
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return;
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}
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dsr = dev->dsr_info.dsr;
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dsr->caps.fw_ver = PVRDMA_FW_VERSION;
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pr_dbg("fw_ver=0x%" PRIx64 "\n", dsr->caps.fw_ver);
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dsr->caps.mode = PVRDMA_DEVICE_MODE_ROCE;
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pr_dbg("mode=%d\n", dsr->caps.mode);
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dsr->caps.gid_types |= PVRDMA_GID_TYPE_FLAG_ROCE_V1;
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pr_dbg("gid_types=0x%x\n", dsr->caps.gid_types);
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dsr->caps.max_uar = RDMA_BAR2_UAR_SIZE;
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pr_dbg("max_uar=%d\n", dsr->caps.max_uar);
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dsr->caps.max_mr_size = dev->dev_attr.max_mr_size;
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dsr->caps.max_qp = dev->dev_attr.max_qp;
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dsr->caps.max_qp_wr = dev->dev_attr.max_qp_wr;
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dsr->caps.max_sge = dev->dev_attr.max_sge;
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dsr->caps.max_cq = dev->dev_attr.max_cq;
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dsr->caps.max_cqe = dev->dev_attr.max_cqe;
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dsr->caps.max_mr = dev->dev_attr.max_mr;
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dsr->caps.max_pd = dev->dev_attr.max_pd;
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dsr->caps.max_ah = dev->dev_attr.max_ah;
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dsr->caps.gid_tbl_len = MAX_GIDS;
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pr_dbg("gid_tbl_len=%d\n", dsr->caps.gid_tbl_len);
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dsr->caps.sys_image_guid = 0;
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pr_dbg("sys_image_guid=%" PRIx64 "\n", dsr->caps.sys_image_guid);
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dsr->caps.node_guid = cpu_to_be64(dev->node_guid);
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pr_dbg("node_guid=%" PRIx64 "\n", be64_to_cpu(dsr->caps.node_guid));
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dsr->caps.phys_port_cnt = MAX_PORTS;
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pr_dbg("phys_port_cnt=%d\n", dsr->caps.phys_port_cnt);
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dsr->caps.max_pkeys = MAX_PKEYS;
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pr_dbg("max_pkeys=%d\n", dsr->caps.max_pkeys);
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pr_dbg("Initialized\n");
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}
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static void init_ports(PVRDMADev *dev, Error **errp)
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{
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int i;
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memset(dev->rdma_dev_res.ports, 0, sizeof(dev->rdma_dev_res.ports));
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for (i = 0; i < MAX_PORTS; i++) {
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dev->rdma_dev_res.ports[i].state = IBV_PORT_DOWN;
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}
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}
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static void uninit_msix(PCIDevice *pdev, int used_vectors)
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{
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PVRDMADev *dev = PVRDMA_DEV(pdev);
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int i;
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for (i = 0; i < used_vectors; i++) {
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msix_vector_unuse(pdev, i);
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}
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msix_uninit(pdev, &dev->msix, &dev->msix);
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}
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static int init_msix(PCIDevice *pdev, Error **errp)
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{
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PVRDMADev *dev = PVRDMA_DEV(pdev);
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int i;
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int rc;
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rc = msix_init(pdev, RDMA_MAX_INTRS, &dev->msix, RDMA_MSIX_BAR_IDX,
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RDMA_MSIX_TABLE, &dev->msix, RDMA_MSIX_BAR_IDX,
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RDMA_MSIX_PBA, 0, NULL);
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if (rc < 0) {
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error_setg(errp, "Failed to initialize MSI-X");
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return rc;
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}
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for (i = 0; i < RDMA_MAX_INTRS; i++) {
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rc = msix_vector_use(PCI_DEVICE(dev), i);
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if (rc < 0) {
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error_setg(errp, "Fail mark MSI-X vector %d", i);
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uninit_msix(pdev, i);
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return rc;
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}
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}
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return 0;
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}
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static void pvrdma_fini(PCIDevice *pdev)
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{
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PVRDMADev *dev = PVRDMA_DEV(pdev);
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pr_dbg("Closing device %s %x.%x\n", pdev->name, PCI_SLOT(pdev->devfn),
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PCI_FUNC(pdev->devfn));
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pvrdma_qp_ops_fini();
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rdma_rm_fini(&dev->rdma_dev_res);
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rdma_backend_fini(&dev->backend_dev);
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free_dsr(dev);
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if (msix_enabled(pdev)) {
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uninit_msix(pdev, RDMA_MAX_INTRS);
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}
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}
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static void pvrdma_stop(PVRDMADev *dev)
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{
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rdma_backend_stop(&dev->backend_dev);
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}
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static void pvrdma_start(PVRDMADev *dev)
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{
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rdma_backend_start(&dev->backend_dev);
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}
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static void activate_device(PVRDMADev *dev)
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{
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pvrdma_start(dev);
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set_reg_val(dev, PVRDMA_REG_ERR, 0);
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pr_dbg("Device activated\n");
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}
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static int unquiesce_device(PVRDMADev *dev)
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{
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pr_dbg("Device unquiesced\n");
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return 0;
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}
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static int reset_device(PVRDMADev *dev)
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{
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pvrdma_stop(dev);
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pr_dbg("Device reset complete\n");
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return 0;
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}
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static uint64_t regs_read(void *opaque, hwaddr addr, unsigned size)
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{
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PVRDMADev *dev = opaque;
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uint32_t val;
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/* pr_dbg("addr=0x%lx, size=%d\n", addr, size); */
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if (get_reg_val(dev, addr, &val)) {
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pr_dbg("Error trying to read REG value from address 0x%x\n",
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(uint32_t)addr);
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return -EINVAL;
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}
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trace_pvrdma_regs_read(addr, val);
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return val;
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}
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static void regs_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
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{
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PVRDMADev *dev = opaque;
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/* pr_dbg("addr=0x%lx, val=0x%x, size=%d\n", addr, (uint32_t)val, size); */
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if (set_reg_val(dev, addr, val)) {
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pr_err("Fail to set REG value, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
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addr, val);
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return;
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}
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trace_pvrdma_regs_write(addr, val);
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switch (addr) {
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case PVRDMA_REG_DSRLOW:
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dev->dsr_info.dma = val;
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break;
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case PVRDMA_REG_DSRHIGH:
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dev->dsr_info.dma |= val << 32;
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load_dsr(dev);
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init_dsr_dev_caps(dev);
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break;
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case PVRDMA_REG_CTL:
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switch (val) {
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case PVRDMA_DEVICE_CTL_ACTIVATE:
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activate_device(dev);
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break;
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case PVRDMA_DEVICE_CTL_UNQUIESCE:
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unquiesce_device(dev);
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break;
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case PVRDMA_DEVICE_CTL_RESET:
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reset_device(dev);
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break;
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}
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break;
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case PVRDMA_REG_IMR:
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pr_dbg("Interrupt mask=0x%" PRIx64 "\n", val);
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dev->interrupt_mask = val;
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break;
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case PVRDMA_REG_REQUEST:
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if (val == 0) {
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execute_command(dev);
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}
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break;
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default:
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break;
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}
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}
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static const MemoryRegionOps regs_ops = {
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.read = regs_read,
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.write = regs_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = sizeof(uint32_t),
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.max_access_size = sizeof(uint32_t),
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},
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};
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static void uar_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
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{
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PVRDMADev *dev = opaque;
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/* pr_dbg("addr=0x%lx, val=0x%x, size=%d\n", addr, (uint32_t)val, size); */
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switch (addr & 0xFFF) { /* Mask with 0xFFF as each UC gets page */
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case PVRDMA_UAR_QP_OFFSET:
|
|
pr_dbg("UAR QP command, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
|
|
(uint64_t)addr, val);
|
|
if (val & PVRDMA_UAR_QP_SEND) {
|
|
pvrdma_qp_send(dev, val & PVRDMA_UAR_HANDLE_MASK);
|
|
}
|
|
if (val & PVRDMA_UAR_QP_RECV) {
|
|
pvrdma_qp_recv(dev, val & PVRDMA_UAR_HANDLE_MASK);
|
|
}
|
|
break;
|
|
case PVRDMA_UAR_CQ_OFFSET:
|
|
/* pr_dbg("UAR CQ cmd, addr=0x%x, val=0x%lx\n", (uint32_t)addr, val); */
|
|
if (val & PVRDMA_UAR_CQ_ARM) {
|
|
rdma_rm_req_notify_cq(&dev->rdma_dev_res,
|
|
val & PVRDMA_UAR_HANDLE_MASK,
|
|
!!(val & PVRDMA_UAR_CQ_ARM_SOL));
|
|
}
|
|
if (val & PVRDMA_UAR_CQ_ARM_SOL) {
|
|
pr_dbg("UAR_CQ_ARM_SOL (%" PRIx64 ")\n",
|
|
val & PVRDMA_UAR_HANDLE_MASK);
|
|
}
|
|
if (val & PVRDMA_UAR_CQ_POLL) {
|
|
pr_dbg("UAR_CQ_POLL (%" PRIx64 ")\n", val & PVRDMA_UAR_HANDLE_MASK);
|
|
pvrdma_cq_poll(&dev->rdma_dev_res, val & PVRDMA_UAR_HANDLE_MASK);
|
|
}
|
|
break;
|
|
default:
|
|
pr_err("Unsupported command, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
|
|
addr, val);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps uar_ops = {
|
|
.write = uar_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.impl = {
|
|
.min_access_size = sizeof(uint32_t),
|
|
.max_access_size = sizeof(uint32_t),
|
|
},
|
|
};
|
|
|
|
static void init_pci_config(PCIDevice *pdev)
|
|
{
|
|
pdev->config[PCI_INTERRUPT_PIN] = 1;
|
|
}
|
|
|
|
static void init_bars(PCIDevice *pdev)
|
|
{
|
|
PVRDMADev *dev = PVRDMA_DEV(pdev);
|
|
|
|
/* BAR 0 - MSI-X */
|
|
memory_region_init(&dev->msix, OBJECT(dev), "pvrdma-msix",
|
|
RDMA_BAR0_MSIX_SIZE);
|
|
pci_register_bar(pdev, RDMA_MSIX_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
|
&dev->msix);
|
|
|
|
/* BAR 1 - Registers */
|
|
memset(&dev->regs_data, 0, sizeof(dev->regs_data));
|
|
memory_region_init_io(&dev->regs, OBJECT(dev), ®s_ops, dev,
|
|
"pvrdma-regs", sizeof(dev->regs_data));
|
|
pci_register_bar(pdev, RDMA_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
|
&dev->regs);
|
|
|
|
/* BAR 2 - UAR */
|
|
memset(&dev->uar_data, 0, sizeof(dev->uar_data));
|
|
memory_region_init_io(&dev->uar, OBJECT(dev), &uar_ops, dev, "rdma-uar",
|
|
sizeof(dev->uar_data));
|
|
pci_register_bar(pdev, RDMA_UAR_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
|
&dev->uar);
|
|
}
|
|
|
|
static void init_regs(PCIDevice *pdev)
|
|
{
|
|
PVRDMADev *dev = PVRDMA_DEV(pdev);
|
|
|
|
set_reg_val(dev, PVRDMA_REG_VERSION, PVRDMA_HW_VERSION);
|
|
set_reg_val(dev, PVRDMA_REG_ERR, 0xFFFF);
|
|
}
|
|
|
|
static void init_dev_caps(PVRDMADev *dev)
|
|
{
|
|
size_t pg_tbl_bytes = TARGET_PAGE_SIZE *
|
|
(TARGET_PAGE_SIZE / sizeof(uint64_t));
|
|
size_t wr_sz = MAX(sizeof(struct pvrdma_sq_wqe_hdr),
|
|
sizeof(struct pvrdma_rq_wqe_hdr));
|
|
|
|
dev->dev_attr.max_qp_wr = pg_tbl_bytes /
|
|
(wr_sz + sizeof(struct pvrdma_sge) * MAX_SGE) -
|
|
TARGET_PAGE_SIZE; /* First page is ring state */
|
|
pr_dbg("max_qp_wr=%d\n", dev->dev_attr.max_qp_wr);
|
|
|
|
dev->dev_attr.max_cqe = pg_tbl_bytes / sizeof(struct pvrdma_cqe) -
|
|
TARGET_PAGE_SIZE; /* First page is ring state */
|
|
pr_dbg("max_cqe=%d\n", dev->dev_attr.max_cqe);
|
|
}
|
|
|
|
static int pvrdma_check_ram_shared(Object *obj, void *opaque)
|
|
{
|
|
bool *shared = opaque;
|
|
|
|
if (object_dynamic_cast(obj, "memory-backend-ram")) {
|
|
*shared = object_property_get_bool(obj, "share", NULL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void pvrdma_realize(PCIDevice *pdev, Error **errp)
|
|
{
|
|
int rc;
|
|
PVRDMADev *dev = PVRDMA_DEV(pdev);
|
|
Object *memdev_root;
|
|
bool ram_shared = false;
|
|
|
|
init_pr_dbg();
|
|
|
|
pr_dbg("Initializing device %s %x.%x\n", pdev->name,
|
|
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
|
|
|
|
if (TARGET_PAGE_SIZE != getpagesize()) {
|
|
error_setg(errp, "Target page size must be the same as host page size");
|
|
return;
|
|
}
|
|
|
|
memdev_root = object_resolve_path("/objects", NULL);
|
|
if (memdev_root) {
|
|
object_child_foreach(memdev_root, pvrdma_check_ram_shared, &ram_shared);
|
|
}
|
|
if (!ram_shared) {
|
|
error_setg(errp, "Only shared memory backed ram is supported");
|
|
return;
|
|
}
|
|
|
|
dev->dsr_info.dsr = NULL;
|
|
|
|
init_pci_config(pdev);
|
|
|
|
init_bars(pdev);
|
|
|
|
init_regs(pdev);
|
|
|
|
init_dev_caps(dev);
|
|
|
|
rc = init_msix(pdev, errp);
|
|
if (rc) {
|
|
goto out;
|
|
}
|
|
|
|
rc = rdma_backend_init(&dev->backend_dev, &dev->rdma_dev_res,
|
|
dev->backend_device_name, dev->backend_port_num,
|
|
dev->backend_gid_idx, &dev->dev_attr, errp);
|
|
if (rc) {
|
|
goto out;
|
|
}
|
|
|
|
rc = rdma_rm_init(&dev->rdma_dev_res, &dev->dev_attr, errp);
|
|
if (rc) {
|
|
goto out;
|
|
}
|
|
|
|
init_ports(dev, errp);
|
|
|
|
rc = pvrdma_qp_ops_init();
|
|
if (rc) {
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
if (rc) {
|
|
error_append_hint(errp, "Device fail to load\n");
|
|
}
|
|
}
|
|
|
|
static void pvrdma_exit(PCIDevice *pdev)
|
|
{
|
|
pvrdma_fini(pdev);
|
|
}
|
|
|
|
static void pvrdma_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
k->realize = pvrdma_realize;
|
|
k->exit = pvrdma_exit;
|
|
k->vendor_id = PCI_VENDOR_ID_VMWARE;
|
|
k->device_id = PCI_DEVICE_ID_VMWARE_PVRDMA;
|
|
k->revision = 0x00;
|
|
k->class_id = PCI_CLASS_NETWORK_OTHER;
|
|
|
|
dc->desc = "RDMA Device";
|
|
dc->props = pvrdma_dev_properties;
|
|
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pvrdma_info = {
|
|
.name = PVRDMA_HW_NAME,
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(PVRDMADev),
|
|
.class_init = pvrdma_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void register_types(void)
|
|
{
|
|
type_register_static(&pvrdma_info);
|
|
}
|
|
|
|
type_init(register_types)
|