qemu/target/riscv
Michael Clark f18637cd61
RISC-V: Add misa runtime write support
This patch adds support for writing misa. misa is validated based
on rules in the ISA specification. 'E' is mutually exclusive with
all other extensions. 'D' depends on 'F' so 'D' bit is dropped
if 'F' is not present. A conservative approach to consistency is
taken by flushing the translation cache on misa writes. misa_mask
is added to the CPU struct to store the original set of extensions.

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11 15:56:22 -08:00
..
Makefile.objs
cpu.c RISC-V: Add misa runtime write support 2019-02-11 15:56:22 -08:00
cpu.h RISC-V: Add misa runtime write support 2019-02-11 15:56:22 -08:00
cpu_bits.h RISC-V: Add misa runtime write support 2019-02-11 15:56:22 -08:00
cpu_helper.c
cpu_user.h
csr.c RISC-V: Add misa runtime write support 2019-02-11 15:56:22 -08:00
fpu_helper.c
gdbstub.c
helper.h
instmap.h
op_helper.c
pmp.c
pmp.h
translate.c