992e5acd4d
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6128 c046a42c-6fe2-441c-8c8c-71466251a162
128 lines
4.2 KiB
C
128 lines
4.2 KiB
C
/*
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* QEMU PowerMac emulation shared definitions and prototypes
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#if !defined(__PPC_MAC_H__)
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#define __PPC_MAC_H__
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1
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#define BIOS_FILENAME "ppc_rom.bin"
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#define VGABIOS_FILENAME "video.x"
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#define NVRAM_SIZE 0x2000
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#define PROM_FILENAME "openbios-ppc32"
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#define PROM_ADDR 0xfff00000
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#define KERNEL_LOAD_ADDR 0x01000000
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#define INITRD_LOAD_ADDR 0x01800000
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/* DBDMA */
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void dbdma_init (int *dbdma_mem_index);
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/* Cuda */
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void cuda_init (int *cuda_mem_index, qemu_irq irq);
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/* MacIO */
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void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
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int dbdma_mem_index, int cuda_mem_index, void *nvram,
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int nb_ide, int *ide_mem_index);
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/* NewWorld PowerMac IDE */
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int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
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/* Heathrow PIC */
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qemu_irq *heathrow_pic_init(int *pmem_index,
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int nb_cpus, qemu_irq **irqs);
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/* Grackle PCI */
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PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
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/* UniNorth PCI */
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PCIBus *pci_pmac_init(qemu_irq *pic);
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/* Mac NVRAM */
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typedef struct MacIONVRAMState MacIONVRAMState;
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MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size);
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void macio_nvram_map (void *opaque, target_phys_addr_t mem_base);
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void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
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uint32_t macio_nvram_read (void *opaque, uint32_t addr);
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void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);
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/* adb.c */
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#define MAX_ADB_DEVICES 16
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#define ADB_MAX_OUT_LEN 16
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typedef struct ADBDevice ADBDevice;
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/* buf = NULL means polling */
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typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
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const uint8_t *buf, int len);
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typedef int ADBDeviceReset(ADBDevice *d);
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struct ADBDevice {
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struct ADBBusState *bus;
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int devaddr;
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int handler;
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ADBDeviceRequest *devreq;
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ADBDeviceReset *devreset;
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void *opaque;
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};
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typedef struct ADBBusState {
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ADBDevice devices[MAX_ADB_DEVICES];
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int nb_devices;
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int poll_index;
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} ADBBusState;
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int adb_request(ADBBusState *s, uint8_t *buf_out,
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const uint8_t *buf, int len);
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int adb_poll(ADBBusState *s, uint8_t *buf_out);
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ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
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ADBDeviceRequest *devreq,
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ADBDeviceReset *devreset,
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void *opaque);
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void adb_kbd_init(ADBBusState *bus);
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void adb_mouse_init(ADBBusState *bus);
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extern ADBBusState adb_bus;
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/* openpic.c */
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/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
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enum {
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OPENPIC_OUTPUT_INT = 0, /* IRQ */
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OPENPIC_OUTPUT_CINT, /* critical IRQ */
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OPENPIC_OUTPUT_MCK, /* Machine check event */
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OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
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OPENPIC_OUTPUT_RESET, /* Core reset event */
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OPENPIC_OUTPUT_NB,
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};
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qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
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qemu_irq **irqs, qemu_irq irq_out);
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#endif /* !defined(__PPC_MAC_H__) */
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