Max Filippov 7c84259019 target-xtensa: add basic checks to dcache opcodes ... Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB, DIWBI, DPFL are privileged), memory accessibility for instructions that reference memory (all DH* and DPFL) and windowed register validity for all data cache instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2014-02-24 04:47:01 +04:00
..
core-dc232b	target-xtensa: add dc232b core	2011-10-16 10:40:02 +00:00
core-dc233c	target-xtensa: add dc233c core	2012-04-15 17:43:16 +00:00
core-fsf	target-xtensa: add fsf core	2011-10-16 10:40:16 +00:00
core-dc232b.c	misc: move include files to include/qemu/	2012-12-19 08:32:39 +01:00
core-dc233c.c	target-xtensa: add missing DEBUG section to dc233c config	2013-11-08 09:26:07 +04:00
core-fsf.c	misc: move include files to include/qemu/	2012-12-19 08:32:39 +01:00
cpu-qom.h	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
cpu.c	cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"	2013-07-29 15:29:15 +02:00
cpu.h	target-xtensa: avoid double-stopping at breakpoints	2013-07-29 18:35:45 +04:00
gdbstub.c	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
helper.c	exec: Make ldl_*_phys input an AddressSpace	2014-02-11 22:56:54 +10:00
helper.h	exec: move include files to include/exec/	2012-12-19 08:31:31 +01:00
Makefile.objs	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
op_helper.c	exec: Make tb_invalidate_phys_addr input an AS	2014-02-11 22:55:55 +10:00
overlay_tool.h	target-xtensa: implement MISC SR	2012-12-08 18:48:26 +00:00
translate.c	target-xtensa: add basic checks to dcache opcodes	2014-02-24 04:47:01 +04:00
xtensa-semi.c	exec: Change cpu_memory_rw_debug() argument to CPUState	2013-07-23 02:41:33 +02:00