c02b37814c
This patch adds migration test support for aarch64. The test code, which implements the same functionality as x86, is booted as a kernel in qemu. Here are the design choices we make for aarch64: * We choose this -kernel approach because aarch64 QEMU doesn't provide a built-in fw like x86 does. So instead of relying on a boot loader, we use -kernel approach for aarch64. * The serial output is sent to PL011 directly. * The physical memory base for mach-virt machine is 0x40000000. We change the start_address and end_address for aarch64. In addition to providing the binary, this patch also includes the source code and the build script in tests/migration/aarch64. So users can change the source and/or re-compile the binary as they wish. Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Wei Huang <wei@redhat.com> Message-Id: <1538669326-28135-1-git-send-email-wei@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
76 lines
1.8 KiB
ArmAsm
76 lines
1.8 KiB
ArmAsm
#
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# Copyright (c) 2018 Red Hat, Inc. and/or its affiliates
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#
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# Author:
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# Wei Huang <wei@redhat.com>
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#
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# This work is licensed under the terms of the GNU GPL, version 2 or later.
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# See the COPYING file in the top-level directory.
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#
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# Note: Please make sure the compiler compiles the assembly code below with
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# pc-relative address. Also the branch instructions should use relative
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# addresses only.
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#include "../migration-test.h"
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.section .text
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.globl _start
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_start:
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/* disable MMU to use phys mem address */
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mrs x0, sctlr_el1
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bic x0, x0, #(1<<0)
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msr sctlr_el1, x0
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isb
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/* traverse test memory region */
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mov x0, #ARM_TEST_MEM_START
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mov x1, #ARM_TEST_MEM_END
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/* output char 'A' to PL011 */
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mov w3, 'A'
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mov x2, #ARM_MACH_VIRT_UART
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strb w3, [x2]
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/* clean up memory */
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mov w3, #0
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mov x4, x0
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clean:
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strb w3, [x4]
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add x4, x4, #TEST_MEM_PAGE_SIZE
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cmp x4, x1
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ble clean
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/* w5 keeps a counter so we can limit the output speed */
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mov w5, #0
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/* main body */
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mainloop:
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mov x4, x0
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innerloop:
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/* increment the first byte of each page by 1 */
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ldrb w3, [x4]
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add w3, w3, #1
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and w3, w3, #0xff
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strb w3, [x4]
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/* make sure QEMU user space can see consistent data as MMU is off */
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dc civac, x4
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add x4, x4, #TEST_MEM_PAGE_SIZE
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cmp x4, x1
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blt innerloop
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add w5, w5, #1
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and w5, w5, #0xff
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cmp w5, #0
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bne mainloop
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/* output char 'B' to PL011 */
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mov w3, 'B'
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strb w3, [x2]
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b mainloop
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