qemu/include/hw/cxl
Jonathan Cameron 7bd1900b36 pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.
As the CXLState will no long be accessible via MachineState
at time of PXB_CXL realization, come back later from the machine specific
code to fill in the missing memory region setup. Only at this stage
is it possible to check if cxl=on, so that check is moved to this
later point.

Note that for multiple host bridges, the allocation order of the
register spaces is changed. This will be reflected in ACPI CEDT.

Stubs are added to handle case of CONFIG_PXB=n for machines that
call these functions.

The bus walking logic is common to all machines so add a utility
function + stub to cxl-host*.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <20220608145440.26106-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09 19:32:49 -04:00
..
cxl_component.h CXL/cxl_component: Add cxl_get_hb_cstate() 2022-05-13 07:57:26 -04:00
cxl_device.h mem/cxl_type3: Add read and write functions for associated hostmem. 2022-05-13 07:57:26 -04:00
cxl_host.h pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup. 2022-06-09 19:32:49 -04:00
cxl_pci.h hw/cxl/device: Add a memory device (8.2.8.5) 2022-05-13 06:13:36 -04:00
cxl.h hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c 2022-06-09 19:32:49 -04:00