6b2b2a703c
The AST2600 has four watchdogs, and they each have a 0x40 of registers. When running as part of an ast2600 system we must check a different offset for the system reset control register in the SCU. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190925143248.10000-12-clg@kaod.org [clg: - reworked model integration into new object class ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
/*
|
|
* ASPEED Watchdog Controller
|
|
*
|
|
* Copyright (C) 2016-2017 IBM Corp.
|
|
*
|
|
* This code is licensed under the GPL version 2 or later. See the
|
|
* COPYING file in the top-level directory.
|
|
*/
|
|
|
|
#ifndef WDT_ASPEED_H
|
|
#define WDT_ASPEED_H
|
|
|
|
#include "hw/misc/aspeed_scu.h"
|
|
#include "hw/sysbus.h"
|
|
|
|
#define TYPE_ASPEED_WDT "aspeed.wdt"
|
|
#define ASPEED_WDT(obj) \
|
|
OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
|
|
#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
|
|
#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
|
|
#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
|
|
|
|
#define ASPEED_WDT_REGS_MAX (0x20 / 4)
|
|
|
|
typedef struct AspeedWDTState {
|
|
/*< private >*/
|
|
SysBusDevice parent_obj;
|
|
QEMUTimer *timer;
|
|
|
|
/*< public >*/
|
|
MemoryRegion iomem;
|
|
uint32_t regs[ASPEED_WDT_REGS_MAX];
|
|
|
|
AspeedSCUState *scu;
|
|
uint32_t pclk_freq;
|
|
} AspeedWDTState;
|
|
|
|
#define ASPEED_WDT_CLASS(klass) \
|
|
OBJECT_CLASS_CHECK(AspeedWDTClass, (klass), TYPE_ASPEED_WDT)
|
|
#define ASPEED_WDT_GET_CLASS(obj) \
|
|
OBJECT_GET_CLASS(AspeedWDTClass, (obj), TYPE_ASPEED_WDT)
|
|
|
|
typedef struct AspeedWDTClass {
|
|
SysBusDeviceClass parent_class;
|
|
|
|
uint32_t offset;
|
|
uint32_t ext_pulse_width_mask;
|
|
uint32_t reset_ctrl_reg;
|
|
void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
|
|
} AspeedWDTClass;
|
|
|
|
#endif /* WDT_ASPEED_H */
|