qemu/accel
Richard Henderson 7b7d00e0a7 cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN
In target/arm we will shortly have "too many" mmu_idx.
The current minimum barrier is caused by the way in which
tlb_flush_page_by_mmuidx is coded.

We can remove this limitation by allocating memory for
consumption by the worker.  Let us assume that this is
the unlikely case, as will be the case for the majority
of targets which have so far satisfied the BUILD_BUG_ON,
and only allocate memory when necessary.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-21 14:18:12 -10:00
..
kvm accel/kvm: Make "kernel_irqchip" default on 2020-01-07 12:08:39 +01:00
stubs kvm: Introduce KVM irqchip change notifier 2019-11-26 10:11:30 +11:00
tcg cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN 2020-01-21 14:18:12 -10:00
accel.c accel: pass object to accel_init_machine 2019-12-17 19:32:27 +01:00
Makefile.objs accel: compile accel/accel.c just once 2019-12-17 19:32:25 +01:00
qtest.c qtest: Don't compile qtest accel on non-POSIX systems 2019-05-02 16:56:33 +02:00