4d2cd2d869
Tests the following for both P9 and P10:
- I2C master POR status
- I2C master status after immediate reset
Tests the following for powernv10-ranier only:
- Config pca9552 hotplug device pins as inputs then
Read the INPUT0/1 registers to verify all pins are high
- Connected GPIO pin tests of P10 PCA9552 device. Tests
output of pins 0-4 affect input of pins 5-9 respectively.
- PCA9554 GPIO pins test. Tests input and ouput functionality.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
122 lines
3.3 KiB
C
122 lines
3.3 KiB
C
/*
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* QTest testcase for PowerNV XSCOM bus
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or
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* later. See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "pnv-xscom.h"
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static uint64_t pnv_xscom_read(QTestState *qts, const PnvChip *chip,
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uint32_t pcba)
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{
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return qtest_readq(qts, pnv_xscom_addr(chip, pcba));
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}
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static void test_xscom_cfam_id(QTestState *qts, const PnvChip *chip)
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{
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uint64_t f000f = pnv_xscom_read(qts, chip, 0xf000f);
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g_assert_cmphex(f000f, ==, chip->cfam_id);
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}
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static void test_cfam_id(const void *data)
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{
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const PnvChip *chip = data;
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const char *machine = "powernv8";
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QTestState *qts;
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if (chip->chip_type == PNV_CHIP_POWER9) {
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machine = "powernv9";
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} else if (chip->chip_type == PNV_CHIP_POWER10) {
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machine = "powernv10";
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}
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qts = qtest_initf("-M %s -accel tcg -cpu %s",
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machine, chip->cpu_model);
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test_xscom_cfam_id(qts, chip);
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qtest_quit(qts);
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}
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#define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
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#define PNV_XSCOM_EX_BASE(core) \
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(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
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#define PNV_XSCOM_P9_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV_XSCOM_P10_EC_BASE(core) \
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((uint64_t)((((core) & ~0x3) + 0x20) << 24) + 0x20000 + \
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(0x1000 << (3 - (core & 0x3))))
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#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
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static void test_xscom_core(QTestState *qts, const PnvChip *chip)
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{
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if (chip->chip_type == PNV_CHIP_POWER10) {
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uint32_t first_core_thread_state =
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PNV_XSCOM_P10_EC_BASE(chip->first_core) + 0x412;
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uint64_t thread_state;
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thread_state = pnv_xscom_read(qts, chip, first_core_thread_state);
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g_assert_cmphex(thread_state, ==, 0);
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} else {
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uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0;
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uint64_t dts0;
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if (chip->chip_type == PNV_CHIP_POWER9) {
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first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core);
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} else { /* POWER8 */
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first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core);
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}
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dts0 = pnv_xscom_read(qts, chip, first_core_dts0);
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g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
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}
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}
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static void test_core(const void *data)
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{
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const PnvChip *chip = data;
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QTestState *qts;
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const char *machine = "powernv8";
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if (chip->chip_type == PNV_CHIP_POWER9) {
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machine = "powernv9";
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} else if (chip->chip_type == PNV_CHIP_POWER10) {
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machine = "powernv10";
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}
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qts = qtest_initf("-M %s -accel tcg -cpu %s",
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machine, chip->cpu_model);
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test_xscom_core(qts, chip);
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qtest_quit(qts);
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}
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static void add_test(const char *name, void (*test)(const void *data))
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(pnv_chips); i++) {
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char *tname = g_strdup_printf("pnv-xscom/%s/%s", name,
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pnv_chips[i].cpu_model);
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qtest_add_data_func(tname, &pnv_chips[i], test);
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g_free(tname);
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}
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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add_test("cfam_id", test_cfam_id);
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add_test("core", test_core);
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return g_test_run();
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}
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