Wilfred Mallawa 7ae7146287 include/hw/riscv/opentitan: update opentitan IRQs ... Updates the opentitan IRQs to match the latest supported commit of Opentitan from TockOS. OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47 Memory layout as per [1] [1] 565e4af397/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-02-07 08:19:22 +10:00
..
boot_opensbi.h	include: Include headers where needed	2023-01-08 01:54:22 -05:00
boot.h	hw/riscv/boot.c: use MachineState in riscv_load_kernel()	2023-01-20 10:14:13 +10:00
microchip_pfsoc.h	include: Include headers where needed	2023-01-08 01:54:22 -05:00
numa.h	hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()	2023-01-20 10:14:14 +10:00
opentitan.h	include/hw/riscv/opentitan: update opentitan IRQs	2023-02-07 08:19:22 +10:00
riscv_hart.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
shakti_c.h	hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0	2023-01-06 10:42:55 +10:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e.h	hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0	2023-01-06 10:42:55 +10:00
sifive_u.h	hw/riscv/sifive_u: use 'fdt' from MachineState	2023-01-20 10:14:13 +10:00
spike.h	hw/riscv/spike: use 'fdt' from MachineState	2023-01-20 10:14:13 +10:00
virt.h	include: Include headers where needed	2023-01-08 01:54:22 -05:00