Taylor Simpson 7aa9ffab79 Hexagon (target/hexagon) load into shifted register instructions ... The following instructions are added L2_loadalignb_io Ryy32 = memb_fifo(Rs32+#s11:1) L2_loadalignh_io Ryy32 = memh_fifo(Rs32+#s11:1) L4_loadalignb_ur Ryy32 = memb_fifo(Rt32<<#u2+#U6) L4_loadalignh_ur Ryy32 = memh_fifo(Rt32<<#u2+#U6) L4_loadalignb_ap Ryy32 = memb_fifo(Re32=#U6) L4_loadalignh_ap Ryy32 = memh_fifo(Re32=#U6) L2_loadalignb_pr Ryy32 = memb_fifo(Rx32++Mu2) L2_loadalignh_pr Ryy32 = memh_fifo(Rx32++Mu2) L2_loadalignb_pbr Ryy32 = memb_fifo(Rx32++Mu2:brev) L2_loadalignh_pbr Ryy32 = memh_fifo(Rx32++Mu2:brev) L2_loadalignb_pi Ryy32 = memb_fifo(Rx32++#s4:1) L2_loadalignh_pi Ryy32 = memh_fifo(Rx32++#s4:1) L2_loadalignb_pci Ryy32 = memb_fifo(Rx32++#s4:1:circ(Mu2)) L2_loadalignh_pci Ryy32 = memh_fifo(Rx32++#s4:1:circ(Mu2)) L2_loadalignb_pcr Ryy32 = memb_fifo(Rx32++I:circ(Mu2)) L2_loadalignh_pcr Ryy32 = memh_fifo(Rx32++I:circ(Mu2)) Test cases in tests/tcg/hexagon/load_align.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-26-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2021-05-01 16:06:11 -07:00
..
allidefs.def
alu.idef	Hexagon (target/hexagon) add A4_addp_c/A4_subp_c	2021-05-01 08:31:43 -07:00
branch.idef
compare.idef	Hexagon (target/hexagon) cleanup ternary operators in semantics	2021-05-01 08:31:43 -07:00
encode_pp.def	Hexagon (target/hexagon) load into shifted register instructions	2021-05-01 16:06:11 -07:00
encode_subinsn.def
encode.def
float.idef	Hexagon (target/hexagon) add F2_sfinvsqrta	2021-05-01 08:31:43 -07:00
iclass.def
ldst.idef	Hexagon (target/hexagon) load into shifted register instructions	2021-05-01 16:06:11 -07:00
macros.def	Hexagon (target/hexagon) bit reverse (brev) addressing	2021-05-01 16:03:10 -07:00
mpy.idef
shift.idef
subinsns.idef
system.idef