Max Chou 7a999d4dd7 target/riscv: rvv: Check single width operator for vector fp widen instructions ... The require_scale_rvf function only checks the double width operator for the vector floating point widen instructions, so most of the widen checking functions need to add require_rvf for single width operator. The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width integer to double width float, so the opfxv_widen_check function doesn’t need require_rvf for the single width operator(integer). Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Cc: qemu-stable <qemu-stable@nongnu.org> Message-ID: <20240322092600.1198921-3-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-06-03 11:12:12 +10:00
..
insn_trans	target/riscv: rvv: Check single width operator for vector fp widen instructions	2024-06-03 11:12:12 +10:00
kvm	target/riscv/kvm: tolerate KVM disable ext errors	2024-06-03 11:12:12 +10:00
tcg	target/riscv: Implement dynamic establishment of custom decoder	2024-06-03 11:12:12 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63	2024-06-03 11:12:11 +10:00
cpu_cfg.h	target/riscv: Add support for Zve64x extension	2024-06-03 11:12:12 +10:00
cpu_helper.c	target/riscv: Add support for Zve32x extension	2024-06-03 11:12:12 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h	target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'	2024-04-26 15:31:37 +02:00
cpu-qom.h	target/riscv: add rv32i, rv32e and rv64e CPUs	2024-02-09 20:49:41 +10:00
cpu.c	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
cpu.h	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
crypto_helper.c
csr.c	target/riscv: Add support for Zve32x extension	2024-06-03 11:12:12 +10:00
debug.c	target/riscv/debug: set tval=pc in breakpoint exceptions	2024-06-03 11:12:12 +10:00
debug.h	exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header	2024-04-26 17:03:05 +02:00
fpu_helper.c
gdbstub.c	target/riscv: Relax vector register check in RISCV gdbstub	2024-06-03 11:12:12 +10:00
helper.h	target/riscv: Raise exceptions on wrs.nto	2024-06-03 11:12:11 +10:00
insn16.decode
insn32.decode	target/riscv: Add support for Zacas extension	2024-01-10 18:47:47 +10:00
instmap.h
internals.h	target/riscv: Use env_archcpu() in [check_]nanbox()	2023-11-07 12:13:27 +01:00
Kconfig	kconfig: express dependency of individual boards on libfdt	2024-05-10 15:45:15 +02:00
m128_helper.c
machine.c	target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit	2024-03-08 20:48:03 +10:00
meson.build	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
monitor.c
op_helper.c	target/riscv: Raise exceptions on wrs.nto	2024-06-03 11:12:11 +10:00
pmp.c	exec/cpu: Extract page-protection definitions to page-protection.h	2024-05-06 11:17:15 +02:00
pmp.h	target/riscv/pmp: Use hwaddr instead of target_ulong for RV32	2024-01-10 18:47:46 +10:00
pmu.c	target/riscv: Add "pmu-mask" property to replace "pmu-num"	2023-11-07 11:06:02 +10:00
pmu.h	target/riscv: Add missing include guard in pmu.h	2024-03-08 16:39:32 +10:00
riscv-qmp-cmds.c	target: Improve error reporting for CpuModelInfo member @props	2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	2024-06-03 11:12:11 +10:00
th_csr.c	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target/riscv: Implement dynamic establishment of custom decoder	2024-06-03 11:12:12 +10:00
vcrypto_helper.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_helper.c	exec/cpu: Extract page-protection definitions to page-protection.h	2024-05-06 11:17:15 +02:00
vector_internals.c	target/riscv: Fix the element agnostic function problem	2024-06-03 11:12:12 +10:00
vector_internals.h	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c