qemu/disas
Helge Deller 2f926bfd5b disas/hppa: Show hexcode of instruction along with disassembly
On hppa many instructions can be expressed by different bytecodes.
To be able to debug qemu translation bugs it's therefore necessary to see the
currently executed byte codes without the need to lookup the sequence without
the full executable.
With this patch the instruction byte code is shown beside the disassembly.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-17 18:36:36 +01:00
..
alpha.c
capstone.c disas: use result of ->read_memory_func 2022-10-06 11:53:40 +01:00
cris.c cris: do not leak struct cris_disasm_data 2019-10-04 18:49:17 +02:00
disas-internal.h disas: Move softmmu specific code to separate file 2023-05-11 09:49:55 +01:00
disas-mon.c disas: Move softmmu specific code to separate file 2023-05-11 09:49:55 +01:00
disas.c disas: Move disas.c into the target-independent source set 2023-05-11 09:51:07 +01:00
hexagon.c Hexagon (disas/hexagon.c) fix memory leak for early exit cases 2021-08-12 09:06:05 -05:00
hppa.c disas/hppa: Show hexcode of instruction along with disassembly 2023-11-17 18:36:36 +01:00
m68k.c disas/m68k: clean up local variable shadowing 2023-09-29 10:07:21 +02:00
meson.build disas/riscv: Add support for XThead* instructions 2023-07-10 22:29:14 +10:00
microblaze.c
mips.c disas/mips: Fix branch displacement for BEQZC and BNEZC 2022-10-31 11:32:07 +01:00
nanomips.c disas/nanomips: Tidy read for 48-bit opcodes 2022-11-08 01:04:25 +01:00
nios2.c disas/nios2: Simplify endianess conversion 2021-10-22 18:07:30 +02:00
riscv-xthead.c disas/riscv: Add support for XThead* instructions 2023-07-10 22:29:14 +10:00
riscv-xthead.h disas/riscv: Add support for XThead* instructions 2023-07-10 22:29:14 +10:00
riscv-xventana.c disas/riscv: Add support for XVentanaCondOps 2023-07-10 22:29:14 +10:00
riscv-xventana.h disas/riscv: Add support for XVentanaCondOps 2023-07-10 22:29:14 +10:00
riscv.c disas/riscv: Replace TABs with space 2023-11-07 11:06:02 +10:00
riscv.h disas/riscv: Add rv_codec_vror_vi for vror.vi 2023-11-07 11:06:02 +10:00
sh4.c disas/sh4: Add missing fallthrough annotations 2020-07-13 11:40:52 +02:00
sparc.c
xtensa.c