ad80e36744
We pass a ResetType argument to the Resettable class enter
phase method, but we don't pass it to hold and exit, even though
the callsites have it readily available. This means that if
a device cared about the ResetType it would need to record it
in the enter phase method to use later on. Pass the type to
all three of the phase methods to avoid having to do that.
Commit created with
for dir in hw target include; do \
spatch --macro-file scripts/cocci-macro-file.h \
--sp-file scripts/coccinelle/reset-type.cocci \
--keep-comments --smpl-spacing --in-place \
--include-headers --dir $dir; done
and no manual edits.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org
134 lines
3.1 KiB
C
134 lines
3.1 KiB
C
/*
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* QEMU IOSB emulation
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*
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* Copyright (c) 2019 Laurent Vivier
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* Copyright (c) 2022 Mark Cave-Ayland
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "migration/vmstate.h"
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#include "hw/sysbus.h"
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#include "hw/misc/iosb.h"
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#include "trace.h"
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#define IOSB_SIZE 0x2000
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#define IOSB_CONFIG 0x0
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#define IOSB_CONFIG2 0x100
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#define IOSB_SONIC_SCSI 0x200
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#define IOSB_REVISION 0x300
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#define IOSB_SCSI_RESID 0x400
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#define IOSB_BRIGHTNESS 0x500
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#define IOSB_TIMEOUT 0x600
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static uint64_t iosb_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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IOSBState *s = IOSB(opaque);
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uint64_t val = 0;
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switch (addr) {
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case IOSB_CONFIG:
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case IOSB_CONFIG2:
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case IOSB_SONIC_SCSI:
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case IOSB_REVISION:
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case IOSB_SCSI_RESID:
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case IOSB_BRIGHTNESS:
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case IOSB_TIMEOUT:
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val = s->regs[addr >> 8];
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "IOSB: unimplemented read addr=0x%"PRIx64
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" val=0x%"PRIx64 " size=%d\n",
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addr, val, size);
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}
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trace_iosb_read(addr, val, size);
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return val;
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}
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static void iosb_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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IOSBState *s = IOSB(opaque);
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switch (addr) {
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case IOSB_CONFIG:
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case IOSB_CONFIG2:
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case IOSB_SONIC_SCSI:
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case IOSB_REVISION:
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case IOSB_SCSI_RESID:
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case IOSB_BRIGHTNESS:
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case IOSB_TIMEOUT:
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s->regs[addr >> 8] = val;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "IOSB: unimplemented write addr=0x%"PRIx64
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" val=0x%"PRIx64 " size=%d\n",
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addr, val, size);
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}
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trace_iosb_write(addr, val, size);
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}
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static const MemoryRegionOps iosb_mmio_ops = {
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.read = iosb_read,
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.write = iosb_write,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void iosb_reset_hold(Object *obj, ResetType type)
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{
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IOSBState *s = IOSB(obj);
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memset(s->regs, 0, sizeof(s->regs));
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/* BCLK 33 MHz */
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s->regs[IOSB_CONFIG >> 8] = 1;
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}
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static void iosb_init(Object *obj)
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{
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IOSBState *s = IOSB(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->mem_regs, obj, &iosb_mmio_ops, s, "IOSB",
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IOSB_SIZE);
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sysbus_init_mmio(sbd, &s->mem_regs);
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}
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static const VMStateDescription vmstate_iosb = {
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.name = "IOSB",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, IOSBState, IOSB_REGS),
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VMSTATE_END_OF_LIST()
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}
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};
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static void iosb_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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ResettableClass *rc = RESETTABLE_CLASS(oc);
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dc->vmsd = &vmstate_iosb;
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rc->phases.hold = iosb_reset_hold;
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}
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static const TypeInfo iosb_info_types[] = {
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{
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.name = TYPE_IOSB,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IOSBState),
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.instance_init = iosb_init,
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.class_init = iosb_class_init,
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},
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};
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DEFINE_TYPES(iosb_info_types)
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