qemu/target/riscv/insn_trans
Philipp Tomsich 79bf3b51ac target/riscv: access configuration through cfg_ptr in DisasContext
The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure.  This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the shallow copies.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-4-philipp.tomsich@vrull.eu>
[ Changes by AF:
 - Fixup checkpatch failures
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16 12:24:18 +10:00
..
trans_privileged.c.inc target/riscv: Sign extend pc for different XLEN 2022-01-21 15:52:57 +10:00
trans_rva.c.inc target/riscv: Calculate address according to XLEN 2022-01-21 15:52:57 +10:00
trans_rvb.c.inc target/riscv: support for 128-bit arithmetic instructions 2022-01-08 15:46:10 +10:00
trans_rvd.c.inc target/riscv: Calculate address according to XLEN 2022-01-21 15:52:57 +10:00
trans_rvf.c.inc target/riscv: Calculate address according to XLEN 2022-01-21 15:52:57 +10:00
trans_rvh.c.inc exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
trans_rvi.c.inc target/riscv: access configuration through cfg_ptr in DisasContext 2022-02-16 12:24:18 +10:00
trans_rvm.c.inc target/riscv: support for 128-bit M extension 2022-01-08 15:46:10 +10:00
trans_rvv.c.inc target/riscv: access configuration through cfg_ptr in DisasContext 2022-02-16 12:24:18 +10:00
trans_rvzfh.c.inc target/riscv: access configuration through cfg_ptr in DisasContext 2022-02-16 12:24:18 +10:00