Jonathan Cameron e967413fe0 hw/cxl: Support 4 HDM decoders at all levels of topology ... Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP and CXL Type 3 end points. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230913132523.29780-5-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2023-10-04 18:15:06 -04:00
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cxl_cdat.h	include/hw/pci: Break inclusion loop pci_bridge.h and cxl.h	2023-01-08 01:54:22 -05:00
cxl_component.h	hw/cxl: Support 4 HDM decoders at all levels of topology	2023-10-04 18:15:06 -04:00
cxl_device.h	hw/cxl/cxl_device: Replace magic number in CXLError definition	2023-09-21 11:31:18 +03:00
cxl_events.h	hw/cxl/events: Add injection of Memory Module Events	2023-06-23 02:54:40 -04:00
cxl_host.h	hw/cxl: Clean up includes	2023-02-08 07:16:23 +01:00
cxl_pci.h	hw/cxl: Clean up includes	2023-02-08 07:16:23 +01:00
cxl.h	hw/cxl: Fix out of bound array access	2023-09-21 11:31:18 +03:00