fa19fe4e3a
To establish performance characteristics of a CXL device when used via a particular CXL topology (root ports, switches, end points) it is necessary to set the appropriate link speed and width in the PCI Express capability structure. Provide x-speed and x-link properties for this. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240916173518.1843023-7-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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| .. | ||
| cxl_downstream.c | ||
| cxl_root_port.c | ||
| cxl_upstream.c | ||
| gen_pcie_root_port.c | ||
| i82801b11.c | ||
| ioh3420.c | ||
| Kconfig | ||
| meson.build | ||
| pci_bridge_dev.c | ||
| pci_expander_bridge_stubs.c | ||
| pci_expander_bridge.c | ||
| pcie_pci_bridge.c | ||
| pcie_root_port.c | ||
| simba.c | ||
| xio3130_downstream.c | ||
| xio3130_upstream.c | ||