0f9668e0c1
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
307 lines
10 KiB
C
307 lines
10 KiB
C
/*
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* QEMU PowerPC 440 Bamboo board emulation
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*
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* Copyright 2007 IBM Corporation.
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* Authors:
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* Jerone Young <jyoung5@us.ibm.com>
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* Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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* Hollis Blanchard <hollisb@us.ibm.com>
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/error-report.h"
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#include "qemu/datadir.h"
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#include "qemu/error-report.h"
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#include "net/net.h"
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#include "hw/pci/pci.h"
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#include "hw/boards.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "sysemu/device_tree.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "hw/char/serial.h"
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#include "hw/ppc/ppc.h"
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#include "ppc405.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/reset.h"
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#include "hw/sysbus.h"
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#include "hw/intc/ppc-uic.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
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/* from u-boot */
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#define KERNEL_ADDR 0x1000000
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#define FDT_ADDR 0x1800000
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#define RAMDISK_ADDR 0x1900000
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#define PPC440EP_PCI_CONFIG 0xeec00000
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#define PPC440EP_PCI_INTACK 0xeed00000
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#define PPC440EP_PCI_SPECIAL 0xeed00000
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#define PPC440EP_PCI_REGS 0xef400000
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#define PPC440EP_PCI_IO 0xe8000000
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#define PPC440EP_PCI_IOLEN 0x00010000
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#define PPC440EP_SDRAM_NR_BANKS 4
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static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
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256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
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};
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static hwaddr entry;
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static int bamboo_load_device_tree(hwaddr addr,
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uint32_t ramsize,
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hwaddr initrd_base,
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hwaddr initrd_size,
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const char *kernel_cmdline)
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{
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int ret = -1;
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uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
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char *filename;
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int fdt_size;
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void *fdt;
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uint32_t tb_freq = 400000000;
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uint32_t clock_freq = 400000000;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
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if (!filename) {
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return -1;
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}
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fdt = load_device_tree(filename, &fdt_size);
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g_free(filename);
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if (fdt == NULL) {
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return -1;
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}
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/* Manipulate device tree in memory. */
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ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
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sizeof(mem_reg_property));
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if (ret < 0)
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fprintf(stderr, "couldn't set /memory/reg\n");
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ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
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initrd_base);
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if (ret < 0)
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fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
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ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
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(initrd_base + initrd_size));
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if (ret < 0)
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fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
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ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
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kernel_cmdline);
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if (ret < 0)
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fprintf(stderr, "couldn't set /chosen/bootargs\n");
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/* Copy data from the host device tree into the guest. Since the guest can
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* directly access the timebase without host involvement, we must expose
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* the correct frequencies. */
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if (kvm_enabled()) {
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tb_freq = kvmppc_get_tbfreq();
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clock_freq = kvmppc_get_clockfreq();
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}
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qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
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clock_freq);
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qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
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tb_freq);
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rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
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g_free(fdt);
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return 0;
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}
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/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
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static void mmubooke_create_initial_mapping(CPUPPCState *env,
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target_ulong va,
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hwaddr pa)
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{
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ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 1U << 31; /* up to 0x80000000 */
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tlb->EPN = va & TARGET_PAGE_MASK;
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tlb->RPN = pa & TARGET_PAGE_MASK;
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tlb->PID = 0;
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tlb = &env->tlb.tlbe[1];
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 1U << 31; /* up to 0xffffffff */
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tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
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tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
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tlb->PID = 0;
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}
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static void main_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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cpu_reset(CPU(cpu));
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env->gpr[1] = (16 * MiB) - 8;
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env->gpr[3] = FDT_ADDR;
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env->nip = entry;
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/* Create a mapping for the kernel. */
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mmubooke_create_initial_mapping(env, 0, 0);
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}
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static void bamboo_init(MachineState *machine)
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{
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *isa = g_new(MemoryRegion, 1);
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MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
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hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
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hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
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PCIBus *pcibus;
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PowerPCCPU *cpu;
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CPUPPCState *env;
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target_long initrd_size = 0;
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DeviceState *dev;
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DeviceState *uicdev;
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SysBusDevice *uicsbd;
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int success;
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int i;
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cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
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env = &cpu->env;
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if (env->mmu_model != POWERPC_MMU_BOOKE) {
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error_report("MMU model %i not supported by this machine",
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env->mmu_model);
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exit(1);
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}
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qemu_register_reset(main_cpu_reset, cpu);
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ppc_booke_timers_init(cpu, 400000000, 0);
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ppc_dcr_init(env, NULL, NULL);
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/* interrupt controller */
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uicdev = qdev_new(TYPE_PPC_UIC);
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uicsbd = SYS_BUS_DEVICE(uicdev);
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object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
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&error_fatal);
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sysbus_realize_and_unref(uicsbd, &error_fatal);
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sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
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((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
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sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
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((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
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/* SDRAM controller */
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memset(ram_bases, 0, sizeof(ram_bases));
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memset(ram_sizes, 0, sizeof(ram_sizes));
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ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
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ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
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/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
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ppc4xx_sdram_init(env,
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qdev_get_gpio_in(uicdev, 14),
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PPC440EP_SDRAM_NR_BANKS, ram_memories,
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ram_bases, ram_sizes, 1);
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/* PCI */
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dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
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PPC440EP_PCI_CONFIG,
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qdev_get_gpio_in(uicdev, pci_irq_nrs[0]),
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qdev_get_gpio_in(uicdev, pci_irq_nrs[1]),
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qdev_get_gpio_in(uicdev, pci_irq_nrs[2]),
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qdev_get_gpio_in(uicdev, pci_irq_nrs[3]),
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NULL);
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pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
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if (!pcibus) {
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error_report("couldn't create PCI controller");
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exit(1);
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}
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memory_region_init_alias(isa, NULL, "isa_mmio",
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get_system_io(), 0, PPC440EP_PCI_IOLEN);
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memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa);
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if (serial_hd(0) != NULL) {
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serial_mm_init(address_space_mem, 0xef600300, 0,
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qdev_get_gpio_in(uicdev, 0),
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PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
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DEVICE_BIG_ENDIAN);
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}
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if (serial_hd(1) != NULL) {
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serial_mm_init(address_space_mem, 0xef600400, 0,
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qdev_get_gpio_in(uicdev, 1),
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PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
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DEVICE_BIG_ENDIAN);
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}
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if (pcibus) {
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/* Register network interfaces. */
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for (i = 0; i < nb_nics; i++) {
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/* There are no PCI NICs on the Bamboo board, but there are
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* PCI slots, so we can pick whatever default model we want. */
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pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL);
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}
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}
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/* Load kernel. */
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if (kernel_filename) {
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hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
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success = load_uimage(kernel_filename, &entry, &loadaddr, NULL,
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NULL, NULL);
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if (success < 0) {
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uint64_t elf_entry;
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success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry,
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NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
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entry = elf_entry;
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}
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/* XXX try again as binary */
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if (success < 0) {
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error_report("could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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}
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/* Load initrd. */
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if (initrd_filename) {
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initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR,
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machine->ram_size - RAMDISK_ADDR);
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if (initrd_size < 0) {
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error_report("could not load ram disk '%s' at %x",
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initrd_filename, RAMDISK_ADDR);
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exit(1);
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}
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}
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/* If we're loading a kernel directly, we must load the device tree too. */
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if (kernel_filename) {
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if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR,
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initrd_size, kernel_cmdline) < 0) {
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error_report("couldn't load device tree");
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exit(1);
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}
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}
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}
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static void bamboo_machine_init(MachineClass *mc)
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{
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mc->desc = "bamboo";
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mc->init = bamboo_init;
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mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb");
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mc->default_ram_id = "ppc4xx.sdram";
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}
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DEFINE_MACHINE("bamboo", bamboo_machine_init)
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