789f4a4c86
This patch includes:
- VMSKLTZ.{B/H/W/D};
- VMSKGEZ.B;
- VMSKNZ.B.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-21-gaosong@loongson.cn>
1094 lines
29 KiB
C
1094 lines
29 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU LoongArch Disassembler
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited.
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*/
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#include "qemu/osdep.h"
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#include "disas/dis-asm.h"
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#include "qemu/bitops.h"
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#include "cpu-csr.h"
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typedef struct {
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disassemble_info *info;
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uint64_t pc;
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uint32_t insn;
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} DisasContext;
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static inline int plus_1(DisasContext *ctx, int x)
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{
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return x + 1;
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}
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static inline int shl_2(DisasContext *ctx, int x)
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{
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return x << 2;
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}
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#define CSR_NAME(REG) \
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[LOONGARCH_CSR_##REG] = (#REG)
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static const char * const csr_names[] = {
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CSR_NAME(CRMD),
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CSR_NAME(PRMD),
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CSR_NAME(EUEN),
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CSR_NAME(MISC),
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CSR_NAME(ECFG),
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CSR_NAME(ESTAT),
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CSR_NAME(ERA),
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CSR_NAME(BADV),
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CSR_NAME(BADI),
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CSR_NAME(EENTRY),
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CSR_NAME(TLBIDX),
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CSR_NAME(TLBEHI),
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CSR_NAME(TLBELO0),
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CSR_NAME(TLBELO1),
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CSR_NAME(ASID),
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CSR_NAME(PGDL),
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CSR_NAME(PGDH),
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CSR_NAME(PGD),
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CSR_NAME(PWCL),
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CSR_NAME(PWCH),
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CSR_NAME(STLBPS),
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CSR_NAME(RVACFG),
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CSR_NAME(CPUID),
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CSR_NAME(PRCFG1),
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CSR_NAME(PRCFG2),
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CSR_NAME(PRCFG3),
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CSR_NAME(SAVE(0)),
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CSR_NAME(SAVE(1)),
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CSR_NAME(SAVE(2)),
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CSR_NAME(SAVE(3)),
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CSR_NAME(SAVE(4)),
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CSR_NAME(SAVE(5)),
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CSR_NAME(SAVE(6)),
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CSR_NAME(SAVE(7)),
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CSR_NAME(SAVE(8)),
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CSR_NAME(SAVE(9)),
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CSR_NAME(SAVE(10)),
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CSR_NAME(SAVE(11)),
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CSR_NAME(SAVE(12)),
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CSR_NAME(SAVE(13)),
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CSR_NAME(SAVE(14)),
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CSR_NAME(SAVE(15)),
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CSR_NAME(TID),
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CSR_NAME(TCFG),
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CSR_NAME(TVAL),
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CSR_NAME(CNTC),
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CSR_NAME(TICLR),
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CSR_NAME(LLBCTL),
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CSR_NAME(IMPCTL1),
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CSR_NAME(IMPCTL2),
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CSR_NAME(TLBRENTRY),
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CSR_NAME(TLBRBADV),
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CSR_NAME(TLBRERA),
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CSR_NAME(TLBRSAVE),
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CSR_NAME(TLBRELO0),
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CSR_NAME(TLBRELO1),
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CSR_NAME(TLBREHI),
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CSR_NAME(TLBRPRMD),
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CSR_NAME(MERRCTL),
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CSR_NAME(MERRINFO1),
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CSR_NAME(MERRINFO2),
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CSR_NAME(MERRENTRY),
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CSR_NAME(MERRERA),
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CSR_NAME(MERRSAVE),
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CSR_NAME(CTAG),
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CSR_NAME(DMW(0)),
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CSR_NAME(DMW(1)),
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CSR_NAME(DMW(2)),
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CSR_NAME(DMW(3)),
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CSR_NAME(DBG),
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CSR_NAME(DERA),
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CSR_NAME(DSAVE),
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};
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static const char *get_csr_name(unsigned num)
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{
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return ((num < ARRAY_SIZE(csr_names)) && (csr_names[num] != NULL)) ?
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csr_names[num] : "Undefined CSR";
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}
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#define output(C, INSN, FMT, ...) \
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{ \
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(C)->info->fprintf_func((C)->info->stream, "%08x %-9s\t" FMT, \
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(C)->insn, INSN, ##__VA_ARGS__); \
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}
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#include "decode-insns.c.inc"
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int print_insn_loongarch(bfd_vma memaddr, struct disassemble_info *info)
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{
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bfd_byte buffer[4];
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uint32_t insn;
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int status;
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status = (*info->read_memory_func)(memaddr, buffer, 4, info);
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if (status != 0) {
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(*info->memory_error_func)(status, memaddr, info);
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return -1;
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}
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insn = bfd_getl32(buffer);
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DisasContext ctx = {
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.info = info,
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.pc = memaddr,
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.insn = insn
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};
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if (!decode(&ctx, insn)) {
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output(&ctx, "illegal", "");
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}
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return 4;
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}
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static void output_r_i(DisasContext *ctx, arg_r_i *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, %d", a->rd, a->imm);
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}
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static void output_rrr(DisasContext *ctx, arg_rrr *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, r%d, r%d", a->rd, a->rj, a->rk);
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}
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static void output_rr_i(DisasContext *ctx, arg_rr_i *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, r%d, %d", a->rd, a->rj, a->imm);
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}
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static void output_rrr_sa(DisasContext *ctx, arg_rrr_sa *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, r%d, r%d, %d", a->rd, a->rj, a->rk, a->sa);
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}
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static void output_rr(DisasContext *ctx, arg_rr *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, r%d", a->rd, a->rj);
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}
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static void output_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, r%d, %d, %d", a->rd, a->rj, a->ms, a->ls);
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}
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static void output_hint_r_i(DisasContext *ctx, arg_hint_r_i *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "%d, r%d, %d", a->hint, a->rj, a->imm);
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}
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static void output_i(DisasContext *ctx, arg_i *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "%d", a->imm);
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}
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static void output_rr_jk(DisasContext *ctx, arg_rr_jk *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, r%d", a->rj, a->rk);
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}
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static void output_ff(DisasContext *ctx, arg_ff *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "f%d, f%d", a->fd, a->fj);
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}
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static void output_fff(DisasContext *ctx, arg_fff *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "f%d, f%d, f%d", a->fd, a->fj, a->fk);
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}
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static void output_ffff(DisasContext *ctx, arg_ffff *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "f%d, f%d, f%d, f%d", a->fd, a->fj, a->fk, a->fa);
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}
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static void output_fffc(DisasContext *ctx, arg_fffc *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "f%d, f%d, f%d, %d", a->fd, a->fj, a->fk, a->ca);
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}
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static void output_fr(DisasContext *ctx, arg_fr *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "f%d, r%d", a->fd, a->rj);
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}
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static void output_rf(DisasContext *ctx, arg_rf *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, f%d", a->rd, a->fj);
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}
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static void output_fcsrd_r(DisasContext *ctx, arg_fcsrd_r *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "fcsr%d, r%d", a->fcsrd, a->rj);
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}
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static void output_r_fcsrs(DisasContext *ctx, arg_r_fcsrs *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, fcsr%d", a->rd, a->fcsrs);
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}
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static void output_cf(DisasContext *ctx, arg_cf *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "fcc%d, f%d", a->cd, a->fj);
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}
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static void output_fc(DisasContext *ctx, arg_fc *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "f%d, fcc%d", a->fd, a->cj);
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}
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static void output_cr(DisasContext *ctx, arg_cr *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "fcc%d, r%d", a->cd, a->rj);
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}
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static void output_rc(DisasContext *ctx, arg_rc *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, fcc%d", a->rd, a->cj);
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}
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static void output_frr(DisasContext *ctx, arg_frr *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "f%d, r%d, r%d", a->fd, a->rj, a->rk);
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}
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static void output_fr_i(DisasContext *ctx, arg_fr_i *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "f%d, r%d, %d", a->fd, a->rj, a->imm);
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}
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static void output_r_offs(DisasContext *ctx, arg_r_offs *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, %d # 0x%" PRIx64, a->rj, a->offs,
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ctx->pc + a->offs);
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}
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static void output_c_offs(DisasContext *ctx, arg_c_offs *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "fcc%d, %d # 0x%" PRIx64, a->cj, a->offs,
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ctx->pc + a->offs);
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}
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static void output_offs(DisasContext *ctx, arg_offs *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "%d # 0x%" PRIx64, a->offs, ctx->pc + a->offs);
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}
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static void output_rr_offs(DisasContext *ctx, arg_rr_offs *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, r%d, %d # 0x%" PRIx64, a->rj,
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a->rd, a->offs, ctx->pc + a->offs);
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}
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static void output_r_csr(DisasContext *ctx, arg_r_csr *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, %d # %s", a->rd, a->csr, get_csr_name(a->csr));
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}
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static void output_rr_csr(DisasContext *ctx, arg_rr_csr *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, r%d, %d # %s",
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a->rd, a->rj, a->csr, get_csr_name(a->csr));
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}
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static void output_empty(DisasContext *ctx, arg_empty *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "");
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}
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static void output_i_rr(DisasContext *ctx, arg_i_rr *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "%d, r%d, r%d", a->imm, a->rj, a->rk);
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}
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static void output_cop_r_i(DisasContext *ctx, arg_cop_r_i *a,
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const char *mnemonic)
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{
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output(ctx, mnemonic, "%d, r%d, %d", a->cop, a->rj, a->imm);
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}
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static void output_j_i(DisasContext *ctx, arg_j_i *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "r%d, %d", a->rj, a->imm);
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}
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#define INSN(insn, type) \
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static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
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{ \
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output_##type(ctx, a, #insn); \
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return true; \
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}
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INSN(clo_w, rr)
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INSN(clz_w, rr)
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INSN(cto_w, rr)
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INSN(ctz_w, rr)
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INSN(clo_d, rr)
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INSN(clz_d, rr)
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INSN(cto_d, rr)
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INSN(ctz_d, rr)
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INSN(revb_2h, rr)
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INSN(revb_4h, rr)
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INSN(revb_2w, rr)
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INSN(revb_d, rr)
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INSN(revh_2w, rr)
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INSN(revh_d, rr)
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INSN(bitrev_4b, rr)
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INSN(bitrev_8b, rr)
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INSN(bitrev_w, rr)
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INSN(bitrev_d, rr)
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INSN(ext_w_h, rr)
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INSN(ext_w_b, rr)
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INSN(rdtimel_w, rr)
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INSN(rdtimeh_w, rr)
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INSN(rdtime_d, rr)
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INSN(cpucfg, rr)
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INSN(asrtle_d, rr_jk)
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INSN(asrtgt_d, rr_jk)
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INSN(alsl_w, rrr_sa)
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INSN(alsl_wu, rrr_sa)
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INSN(bytepick_w, rrr_sa)
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INSN(bytepick_d, rrr_sa)
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INSN(add_w, rrr)
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INSN(add_d, rrr)
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INSN(sub_w, rrr)
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INSN(sub_d, rrr)
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INSN(slt, rrr)
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INSN(sltu, rrr)
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INSN(maskeqz, rrr)
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INSN(masknez, rrr)
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INSN(nor, rrr)
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INSN(and, rrr)
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INSN(or, rrr)
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INSN(xor, rrr)
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INSN(orn, rrr)
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INSN(andn, rrr)
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INSN(sll_w, rrr)
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INSN(srl_w, rrr)
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INSN(sra_w, rrr)
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INSN(sll_d, rrr)
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INSN(srl_d, rrr)
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INSN(sra_d, rrr)
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INSN(rotr_w, rrr)
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INSN(rotr_d, rrr)
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INSN(mul_w, rrr)
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INSN(mulh_w, rrr)
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INSN(mulh_wu, rrr)
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INSN(mul_d, rrr)
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INSN(mulh_d, rrr)
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INSN(mulh_du, rrr)
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INSN(mulw_d_w, rrr)
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INSN(mulw_d_wu, rrr)
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INSN(div_w, rrr)
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INSN(mod_w, rrr)
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INSN(div_wu, rrr)
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INSN(mod_wu, rrr)
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INSN(div_d, rrr)
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INSN(mod_d, rrr)
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INSN(div_du, rrr)
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INSN(mod_du, rrr)
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INSN(crc_w_b_w, rrr)
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INSN(crc_w_h_w, rrr)
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INSN(crc_w_w_w, rrr)
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INSN(crc_w_d_w, rrr)
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INSN(crcc_w_b_w, rrr)
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INSN(crcc_w_h_w, rrr)
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INSN(crcc_w_w_w, rrr)
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INSN(crcc_w_d_w, rrr)
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INSN(break, i)
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INSN(syscall, i)
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INSN(alsl_d, rrr_sa)
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INSN(slli_w, rr_i)
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INSN(slli_d, rr_i)
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INSN(srli_w, rr_i)
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INSN(srli_d, rr_i)
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INSN(srai_w, rr_i)
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INSN(srai_d, rr_i)
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INSN(rotri_w, rr_i)
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INSN(rotri_d, rr_i)
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INSN(bstrins_w, rr_ms_ls)
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INSN(bstrpick_w, rr_ms_ls)
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INSN(bstrins_d, rr_ms_ls)
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INSN(bstrpick_d, rr_ms_ls)
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INSN(fadd_s, fff)
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INSN(fadd_d, fff)
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INSN(fsub_s, fff)
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INSN(fsub_d, fff)
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INSN(fmul_s, fff)
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INSN(fmul_d, fff)
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INSN(fdiv_s, fff)
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INSN(fdiv_d, fff)
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INSN(fmax_s, fff)
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INSN(fmax_d, fff)
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INSN(fmin_s, fff)
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INSN(fmin_d, fff)
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INSN(fmaxa_s, fff)
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INSN(fmaxa_d, fff)
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INSN(fmina_s, fff)
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INSN(fmina_d, fff)
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INSN(fscaleb_s, fff)
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INSN(fscaleb_d, fff)
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INSN(fcopysign_s, fff)
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INSN(fcopysign_d, fff)
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INSN(fabs_s, ff)
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INSN(fabs_d, ff)
|
|
INSN(fneg_s, ff)
|
|
INSN(fneg_d, ff)
|
|
INSN(flogb_s, ff)
|
|
INSN(flogb_d, ff)
|
|
INSN(fclass_s, ff)
|
|
INSN(fclass_d, ff)
|
|
INSN(fsqrt_s, ff)
|
|
INSN(fsqrt_d, ff)
|
|
INSN(frecip_s, ff)
|
|
INSN(frecip_d, ff)
|
|
INSN(frsqrt_s, ff)
|
|
INSN(frsqrt_d, ff)
|
|
INSN(fmov_s, ff)
|
|
INSN(fmov_d, ff)
|
|
INSN(movgr2fr_w, fr)
|
|
INSN(movgr2fr_d, fr)
|
|
INSN(movgr2frh_w, fr)
|
|
INSN(movfr2gr_s, rf)
|
|
INSN(movfr2gr_d, rf)
|
|
INSN(movfrh2gr_s, rf)
|
|
INSN(movgr2fcsr, fcsrd_r)
|
|
INSN(movfcsr2gr, r_fcsrs)
|
|
INSN(movfr2cf, cf)
|
|
INSN(movcf2fr, fc)
|
|
INSN(movgr2cf, cr)
|
|
INSN(movcf2gr, rc)
|
|
INSN(fcvt_s_d, ff)
|
|
INSN(fcvt_d_s, ff)
|
|
INSN(ftintrm_w_s, ff)
|
|
INSN(ftintrm_w_d, ff)
|
|
INSN(ftintrm_l_s, ff)
|
|
INSN(ftintrm_l_d, ff)
|
|
INSN(ftintrp_w_s, ff)
|
|
INSN(ftintrp_w_d, ff)
|
|
INSN(ftintrp_l_s, ff)
|
|
INSN(ftintrp_l_d, ff)
|
|
INSN(ftintrz_w_s, ff)
|
|
INSN(ftintrz_w_d, ff)
|
|
INSN(ftintrz_l_s, ff)
|
|
INSN(ftintrz_l_d, ff)
|
|
INSN(ftintrne_w_s, ff)
|
|
INSN(ftintrne_w_d, ff)
|
|
INSN(ftintrne_l_s, ff)
|
|
INSN(ftintrne_l_d, ff)
|
|
INSN(ftint_w_s, ff)
|
|
INSN(ftint_w_d, ff)
|
|
INSN(ftint_l_s, ff)
|
|
INSN(ftint_l_d, ff)
|
|
INSN(ffint_s_w, ff)
|
|
INSN(ffint_s_l, ff)
|
|
INSN(ffint_d_w, ff)
|
|
INSN(ffint_d_l, ff)
|
|
INSN(frint_s, ff)
|
|
INSN(frint_d, ff)
|
|
INSN(slti, rr_i)
|
|
INSN(sltui, rr_i)
|
|
INSN(addi_w, rr_i)
|
|
INSN(addi_d, rr_i)
|
|
INSN(lu52i_d, rr_i)
|
|
INSN(andi, rr_i)
|
|
INSN(ori, rr_i)
|
|
INSN(xori, rr_i)
|
|
INSN(fmadd_s, ffff)
|
|
INSN(fmadd_d, ffff)
|
|
INSN(fmsub_s, ffff)
|
|
INSN(fmsub_d, ffff)
|
|
INSN(fnmadd_s, ffff)
|
|
INSN(fnmadd_d, ffff)
|
|
INSN(fnmsub_s, ffff)
|
|
INSN(fnmsub_d, ffff)
|
|
INSN(fsel, fffc)
|
|
INSN(addu16i_d, rr_i)
|
|
INSN(lu12i_w, r_i)
|
|
INSN(lu32i_d, r_i)
|
|
INSN(ll_w, rr_i)
|
|
INSN(sc_w, rr_i)
|
|
INSN(ll_d, rr_i)
|
|
INSN(sc_d, rr_i)
|
|
INSN(ldptr_w, rr_i)
|
|
INSN(stptr_w, rr_i)
|
|
INSN(ldptr_d, rr_i)
|
|
INSN(stptr_d, rr_i)
|
|
INSN(ld_b, rr_i)
|
|
INSN(ld_h, rr_i)
|
|
INSN(ld_w, rr_i)
|
|
INSN(ld_d, rr_i)
|
|
INSN(st_b, rr_i)
|
|
INSN(st_h, rr_i)
|
|
INSN(st_w, rr_i)
|
|
INSN(st_d, rr_i)
|
|
INSN(ld_bu, rr_i)
|
|
INSN(ld_hu, rr_i)
|
|
INSN(ld_wu, rr_i)
|
|
INSN(preld, hint_r_i)
|
|
INSN(fld_s, fr_i)
|
|
INSN(fst_s, fr_i)
|
|
INSN(fld_d, fr_i)
|
|
INSN(fst_d, fr_i)
|
|
INSN(ldx_b, rrr)
|
|
INSN(ldx_h, rrr)
|
|
INSN(ldx_w, rrr)
|
|
INSN(ldx_d, rrr)
|
|
INSN(stx_b, rrr)
|
|
INSN(stx_h, rrr)
|
|
INSN(stx_w, rrr)
|
|
INSN(stx_d, rrr)
|
|
INSN(ldx_bu, rrr)
|
|
INSN(ldx_hu, rrr)
|
|
INSN(ldx_wu, rrr)
|
|
INSN(fldx_s, frr)
|
|
INSN(fldx_d, frr)
|
|
INSN(fstx_s, frr)
|
|
INSN(fstx_d, frr)
|
|
INSN(amswap_w, rrr)
|
|
INSN(amswap_d, rrr)
|
|
INSN(amadd_w, rrr)
|
|
INSN(amadd_d, rrr)
|
|
INSN(amand_w, rrr)
|
|
INSN(amand_d, rrr)
|
|
INSN(amor_w, rrr)
|
|
INSN(amor_d, rrr)
|
|
INSN(amxor_w, rrr)
|
|
INSN(amxor_d, rrr)
|
|
INSN(ammax_w, rrr)
|
|
INSN(ammax_d, rrr)
|
|
INSN(ammin_w, rrr)
|
|
INSN(ammin_d, rrr)
|
|
INSN(ammax_wu, rrr)
|
|
INSN(ammax_du, rrr)
|
|
INSN(ammin_wu, rrr)
|
|
INSN(ammin_du, rrr)
|
|
INSN(amswap_db_w, rrr)
|
|
INSN(amswap_db_d, rrr)
|
|
INSN(amadd_db_w, rrr)
|
|
INSN(amadd_db_d, rrr)
|
|
INSN(amand_db_w, rrr)
|
|
INSN(amand_db_d, rrr)
|
|
INSN(amor_db_w, rrr)
|
|
INSN(amor_db_d, rrr)
|
|
INSN(amxor_db_w, rrr)
|
|
INSN(amxor_db_d, rrr)
|
|
INSN(ammax_db_w, rrr)
|
|
INSN(ammax_db_d, rrr)
|
|
INSN(ammin_db_w, rrr)
|
|
INSN(ammin_db_d, rrr)
|
|
INSN(ammax_db_wu, rrr)
|
|
INSN(ammax_db_du, rrr)
|
|
INSN(ammin_db_wu, rrr)
|
|
INSN(ammin_db_du, rrr)
|
|
INSN(dbar, i)
|
|
INSN(ibar, i)
|
|
INSN(fldgt_s, frr)
|
|
INSN(fldgt_d, frr)
|
|
INSN(fldle_s, frr)
|
|
INSN(fldle_d, frr)
|
|
INSN(fstgt_s, frr)
|
|
INSN(fstgt_d, frr)
|
|
INSN(fstle_s, frr)
|
|
INSN(fstle_d, frr)
|
|
INSN(ldgt_b, rrr)
|
|
INSN(ldgt_h, rrr)
|
|
INSN(ldgt_w, rrr)
|
|
INSN(ldgt_d, rrr)
|
|
INSN(ldle_b, rrr)
|
|
INSN(ldle_h, rrr)
|
|
INSN(ldle_w, rrr)
|
|
INSN(ldle_d, rrr)
|
|
INSN(stgt_b, rrr)
|
|
INSN(stgt_h, rrr)
|
|
INSN(stgt_w, rrr)
|
|
INSN(stgt_d, rrr)
|
|
INSN(stle_b, rrr)
|
|
INSN(stle_h, rrr)
|
|
INSN(stle_w, rrr)
|
|
INSN(stle_d, rrr)
|
|
INSN(beqz, r_offs)
|
|
INSN(bnez, r_offs)
|
|
INSN(bceqz, c_offs)
|
|
INSN(bcnez, c_offs)
|
|
INSN(jirl, rr_i)
|
|
INSN(b, offs)
|
|
INSN(bl, offs)
|
|
INSN(beq, rr_offs)
|
|
INSN(bne, rr_offs)
|
|
INSN(blt, rr_offs)
|
|
INSN(bge, rr_offs)
|
|
INSN(bltu, rr_offs)
|
|
INSN(bgeu, rr_offs)
|
|
INSN(csrrd, r_csr)
|
|
INSN(csrwr, r_csr)
|
|
INSN(csrxchg, rr_csr)
|
|
INSN(iocsrrd_b, rr)
|
|
INSN(iocsrrd_h, rr)
|
|
INSN(iocsrrd_w, rr)
|
|
INSN(iocsrrd_d, rr)
|
|
INSN(iocsrwr_b, rr)
|
|
INSN(iocsrwr_h, rr)
|
|
INSN(iocsrwr_w, rr)
|
|
INSN(iocsrwr_d, rr)
|
|
INSN(tlbsrch, empty)
|
|
INSN(tlbrd, empty)
|
|
INSN(tlbwr, empty)
|
|
INSN(tlbfill, empty)
|
|
INSN(tlbclr, empty)
|
|
INSN(tlbflush, empty)
|
|
INSN(invtlb, i_rr)
|
|
INSN(cacop, cop_r_i)
|
|
INSN(lddir, rr_i)
|
|
INSN(ldpte, j_i)
|
|
INSN(ertn, empty)
|
|
INSN(idle, i)
|
|
INSN(dbcl, i)
|
|
|
|
#define output_fcmp(C, PREFIX, SUFFIX) \
|
|
{ \
|
|
(C)->info->fprintf_func((C)->info->stream, "%08x %s%s\tfcc%d, f%d, f%d", \
|
|
(C)->insn, PREFIX, SUFFIX, a->cd, \
|
|
a->fj, a->fk); \
|
|
}
|
|
|
|
static bool output_cff_fcond(DisasContext *ctx, arg_cff_fcond * a,
|
|
const char *suffix)
|
|
{
|
|
bool ret = true;
|
|
switch (a->fcond) {
|
|
case 0x0:
|
|
output_fcmp(ctx, "fcmp_caf_", suffix);
|
|
break;
|
|
case 0x1:
|
|
output_fcmp(ctx, "fcmp_saf_", suffix);
|
|
break;
|
|
case 0x2:
|
|
output_fcmp(ctx, "fcmp_clt_", suffix);
|
|
break;
|
|
case 0x3:
|
|
output_fcmp(ctx, "fcmp_slt_", suffix);
|
|
break;
|
|
case 0x4:
|
|
output_fcmp(ctx, "fcmp_ceq_", suffix);
|
|
break;
|
|
case 0x5:
|
|
output_fcmp(ctx, "fcmp_seq_", suffix);
|
|
break;
|
|
case 0x6:
|
|
output_fcmp(ctx, "fcmp_cle_", suffix);
|
|
break;
|
|
case 0x7:
|
|
output_fcmp(ctx, "fcmp_sle_", suffix);
|
|
break;
|
|
case 0x8:
|
|
output_fcmp(ctx, "fcmp_cun_", suffix);
|
|
break;
|
|
case 0x9:
|
|
output_fcmp(ctx, "fcmp_sun_", suffix);
|
|
break;
|
|
case 0xA:
|
|
output_fcmp(ctx, "fcmp_cult_", suffix);
|
|
break;
|
|
case 0xB:
|
|
output_fcmp(ctx, "fcmp_sult_", suffix);
|
|
break;
|
|
case 0xC:
|
|
output_fcmp(ctx, "fcmp_cueq_", suffix);
|
|
break;
|
|
case 0xD:
|
|
output_fcmp(ctx, "fcmp_sueq_", suffix);
|
|
break;
|
|
case 0xE:
|
|
output_fcmp(ctx, "fcmp_cule_", suffix);
|
|
break;
|
|
case 0xF:
|
|
output_fcmp(ctx, "fcmp_sule_", suffix);
|
|
break;
|
|
case 0x10:
|
|
output_fcmp(ctx, "fcmp_cne_", suffix);
|
|
break;
|
|
case 0x11:
|
|
output_fcmp(ctx, "fcmp_sne_", suffix);
|
|
break;
|
|
case 0x14:
|
|
output_fcmp(ctx, "fcmp_cor_", suffix);
|
|
break;
|
|
case 0x15:
|
|
output_fcmp(ctx, "fcmp_sor_", suffix);
|
|
break;
|
|
case 0x18:
|
|
output_fcmp(ctx, "fcmp_cune_", suffix);
|
|
break;
|
|
case 0x19:
|
|
output_fcmp(ctx, "fcmp_sune_", suffix);
|
|
break;
|
|
default:
|
|
ret = false;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
#define FCMP_INSN(suffix) \
|
|
static bool trans_fcmp_cond_##suffix(DisasContext *ctx, \
|
|
arg_cff_fcond * a) \
|
|
{ \
|
|
return output_cff_fcond(ctx, a, #suffix); \
|
|
}
|
|
|
|
FCMP_INSN(s)
|
|
FCMP_INSN(d)
|
|
|
|
#define PCADD_INSN(name) \
|
|
static bool trans_##name(DisasContext *ctx, arg_##name *a) \
|
|
{ \
|
|
output(ctx, #name, "r%d, %d # 0x%" PRIx64, \
|
|
a->rd, a->imm, gen_##name(ctx->pc, a->imm)); \
|
|
return true; \
|
|
}
|
|
|
|
static uint64_t gen_pcaddi(uint64_t pc, int imm)
|
|
{
|
|
return pc + (imm << 2);
|
|
}
|
|
|
|
static uint64_t gen_pcalau12i(uint64_t pc, int imm)
|
|
{
|
|
return (pc + (imm << 12)) & ~0xfff;
|
|
}
|
|
|
|
static uint64_t gen_pcaddu12i(uint64_t pc, int imm)
|
|
{
|
|
return pc + (imm << 12);
|
|
}
|
|
|
|
static uint64_t gen_pcaddu18i(uint64_t pc, int imm)
|
|
{
|
|
return pc + ((uint64_t)(imm) << 18);
|
|
}
|
|
|
|
PCADD_INSN(pcaddi)
|
|
PCADD_INSN(pcalau12i)
|
|
PCADD_INSN(pcaddu12i)
|
|
PCADD_INSN(pcaddu18i)
|
|
|
|
#define INSN_LSX(insn, type) \
|
|
static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
|
|
{ \
|
|
output_##type(ctx, a, #insn); \
|
|
return true; \
|
|
}
|
|
|
|
static void output_vvv(DisasContext *ctx, arg_vvv *a, const char *mnemonic)
|
|
{
|
|
output(ctx, mnemonic, "v%d, v%d, v%d", a->vd, a->vj, a->vk);
|
|
}
|
|
|
|
static void output_vv_i(DisasContext *ctx, arg_vv_i *a, const char *mnemonic)
|
|
{
|
|
output(ctx, mnemonic, "v%d, v%d, 0x%x", a->vd, a->vj, a->imm);
|
|
}
|
|
|
|
static void output_vv(DisasContext *ctx, arg_vv *a, const char *mnemonic)
|
|
{
|
|
output(ctx, mnemonic, "v%d, v%d", a->vd, a->vj);
|
|
}
|
|
|
|
INSN_LSX(vadd_b, vvv)
|
|
INSN_LSX(vadd_h, vvv)
|
|
INSN_LSX(vadd_w, vvv)
|
|
INSN_LSX(vadd_d, vvv)
|
|
INSN_LSX(vadd_q, vvv)
|
|
INSN_LSX(vsub_b, vvv)
|
|
INSN_LSX(vsub_h, vvv)
|
|
INSN_LSX(vsub_w, vvv)
|
|
INSN_LSX(vsub_d, vvv)
|
|
INSN_LSX(vsub_q, vvv)
|
|
|
|
INSN_LSX(vaddi_bu, vv_i)
|
|
INSN_LSX(vaddi_hu, vv_i)
|
|
INSN_LSX(vaddi_wu, vv_i)
|
|
INSN_LSX(vaddi_du, vv_i)
|
|
INSN_LSX(vsubi_bu, vv_i)
|
|
INSN_LSX(vsubi_hu, vv_i)
|
|
INSN_LSX(vsubi_wu, vv_i)
|
|
INSN_LSX(vsubi_du, vv_i)
|
|
|
|
INSN_LSX(vneg_b, vv)
|
|
INSN_LSX(vneg_h, vv)
|
|
INSN_LSX(vneg_w, vv)
|
|
INSN_LSX(vneg_d, vv)
|
|
|
|
INSN_LSX(vsadd_b, vvv)
|
|
INSN_LSX(vsadd_h, vvv)
|
|
INSN_LSX(vsadd_w, vvv)
|
|
INSN_LSX(vsadd_d, vvv)
|
|
INSN_LSX(vsadd_bu, vvv)
|
|
INSN_LSX(vsadd_hu, vvv)
|
|
INSN_LSX(vsadd_wu, vvv)
|
|
INSN_LSX(vsadd_du, vvv)
|
|
INSN_LSX(vssub_b, vvv)
|
|
INSN_LSX(vssub_h, vvv)
|
|
INSN_LSX(vssub_w, vvv)
|
|
INSN_LSX(vssub_d, vvv)
|
|
INSN_LSX(vssub_bu, vvv)
|
|
INSN_LSX(vssub_hu, vvv)
|
|
INSN_LSX(vssub_wu, vvv)
|
|
INSN_LSX(vssub_du, vvv)
|
|
|
|
INSN_LSX(vhaddw_h_b, vvv)
|
|
INSN_LSX(vhaddw_w_h, vvv)
|
|
INSN_LSX(vhaddw_d_w, vvv)
|
|
INSN_LSX(vhaddw_q_d, vvv)
|
|
INSN_LSX(vhaddw_hu_bu, vvv)
|
|
INSN_LSX(vhaddw_wu_hu, vvv)
|
|
INSN_LSX(vhaddw_du_wu, vvv)
|
|
INSN_LSX(vhaddw_qu_du, vvv)
|
|
INSN_LSX(vhsubw_h_b, vvv)
|
|
INSN_LSX(vhsubw_w_h, vvv)
|
|
INSN_LSX(vhsubw_d_w, vvv)
|
|
INSN_LSX(vhsubw_q_d, vvv)
|
|
INSN_LSX(vhsubw_hu_bu, vvv)
|
|
INSN_LSX(vhsubw_wu_hu, vvv)
|
|
INSN_LSX(vhsubw_du_wu, vvv)
|
|
INSN_LSX(vhsubw_qu_du, vvv)
|
|
|
|
INSN_LSX(vaddwev_h_b, vvv)
|
|
INSN_LSX(vaddwev_w_h, vvv)
|
|
INSN_LSX(vaddwev_d_w, vvv)
|
|
INSN_LSX(vaddwev_q_d, vvv)
|
|
INSN_LSX(vaddwod_h_b, vvv)
|
|
INSN_LSX(vaddwod_w_h, vvv)
|
|
INSN_LSX(vaddwod_d_w, vvv)
|
|
INSN_LSX(vaddwod_q_d, vvv)
|
|
INSN_LSX(vsubwev_h_b, vvv)
|
|
INSN_LSX(vsubwev_w_h, vvv)
|
|
INSN_LSX(vsubwev_d_w, vvv)
|
|
INSN_LSX(vsubwev_q_d, vvv)
|
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INSN_LSX(vsubwod_h_b, vvv)
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INSN_LSX(vsubwod_w_h, vvv)
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INSN_LSX(vsubwod_d_w, vvv)
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INSN_LSX(vsubwod_q_d, vvv)
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INSN_LSX(vaddwev_h_bu, vvv)
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INSN_LSX(vaddwev_w_hu, vvv)
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INSN_LSX(vaddwev_d_wu, vvv)
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INSN_LSX(vaddwev_q_du, vvv)
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INSN_LSX(vaddwod_h_bu, vvv)
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INSN_LSX(vaddwod_w_hu, vvv)
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INSN_LSX(vaddwod_d_wu, vvv)
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INSN_LSX(vaddwod_q_du, vvv)
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INSN_LSX(vsubwev_h_bu, vvv)
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INSN_LSX(vsubwev_w_hu, vvv)
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INSN_LSX(vsubwev_d_wu, vvv)
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INSN_LSX(vsubwev_q_du, vvv)
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INSN_LSX(vsubwod_h_bu, vvv)
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INSN_LSX(vsubwod_w_hu, vvv)
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INSN_LSX(vsubwod_d_wu, vvv)
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INSN_LSX(vsubwod_q_du, vvv)
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INSN_LSX(vaddwev_h_bu_b, vvv)
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INSN_LSX(vaddwev_w_hu_h, vvv)
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INSN_LSX(vaddwev_d_wu_w, vvv)
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INSN_LSX(vaddwev_q_du_d, vvv)
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INSN_LSX(vaddwod_h_bu_b, vvv)
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INSN_LSX(vaddwod_w_hu_h, vvv)
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INSN_LSX(vaddwod_d_wu_w, vvv)
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INSN_LSX(vaddwod_q_du_d, vvv)
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INSN_LSX(vavg_b, vvv)
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INSN_LSX(vavg_h, vvv)
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INSN_LSX(vavg_w, vvv)
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INSN_LSX(vavg_d, vvv)
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INSN_LSX(vavg_bu, vvv)
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INSN_LSX(vavg_hu, vvv)
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INSN_LSX(vavg_wu, vvv)
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INSN_LSX(vavg_du, vvv)
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INSN_LSX(vavgr_b, vvv)
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INSN_LSX(vavgr_h, vvv)
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INSN_LSX(vavgr_w, vvv)
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INSN_LSX(vavgr_d, vvv)
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INSN_LSX(vavgr_bu, vvv)
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INSN_LSX(vavgr_hu, vvv)
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INSN_LSX(vavgr_wu, vvv)
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INSN_LSX(vavgr_du, vvv)
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INSN_LSX(vabsd_b, vvv)
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INSN_LSX(vabsd_h, vvv)
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INSN_LSX(vabsd_w, vvv)
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INSN_LSX(vabsd_d, vvv)
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INSN_LSX(vabsd_bu, vvv)
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INSN_LSX(vabsd_hu, vvv)
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INSN_LSX(vabsd_wu, vvv)
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INSN_LSX(vabsd_du, vvv)
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INSN_LSX(vadda_b, vvv)
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INSN_LSX(vadda_h, vvv)
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INSN_LSX(vadda_w, vvv)
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INSN_LSX(vadda_d, vvv)
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INSN_LSX(vmax_b, vvv)
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INSN_LSX(vmax_h, vvv)
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INSN_LSX(vmax_w, vvv)
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INSN_LSX(vmax_d, vvv)
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INSN_LSX(vmin_b, vvv)
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INSN_LSX(vmin_h, vvv)
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INSN_LSX(vmin_w, vvv)
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INSN_LSX(vmin_d, vvv)
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INSN_LSX(vmax_bu, vvv)
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INSN_LSX(vmax_hu, vvv)
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INSN_LSX(vmax_wu, vvv)
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INSN_LSX(vmax_du, vvv)
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INSN_LSX(vmin_bu, vvv)
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INSN_LSX(vmin_hu, vvv)
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INSN_LSX(vmin_wu, vvv)
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INSN_LSX(vmin_du, vvv)
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INSN_LSX(vmaxi_b, vv_i)
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INSN_LSX(vmaxi_h, vv_i)
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INSN_LSX(vmaxi_w, vv_i)
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INSN_LSX(vmaxi_d, vv_i)
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INSN_LSX(vmini_b, vv_i)
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INSN_LSX(vmini_h, vv_i)
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INSN_LSX(vmini_w, vv_i)
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INSN_LSX(vmini_d, vv_i)
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INSN_LSX(vmaxi_bu, vv_i)
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INSN_LSX(vmaxi_hu, vv_i)
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INSN_LSX(vmaxi_wu, vv_i)
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INSN_LSX(vmaxi_du, vv_i)
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INSN_LSX(vmini_bu, vv_i)
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INSN_LSX(vmini_hu, vv_i)
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INSN_LSX(vmini_wu, vv_i)
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INSN_LSX(vmini_du, vv_i)
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INSN_LSX(vmul_b, vvv)
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INSN_LSX(vmul_h, vvv)
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INSN_LSX(vmul_w, vvv)
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INSN_LSX(vmul_d, vvv)
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INSN_LSX(vmuh_b, vvv)
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INSN_LSX(vmuh_h, vvv)
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INSN_LSX(vmuh_w, vvv)
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INSN_LSX(vmuh_d, vvv)
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INSN_LSX(vmuh_bu, vvv)
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INSN_LSX(vmuh_hu, vvv)
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INSN_LSX(vmuh_wu, vvv)
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INSN_LSX(vmuh_du, vvv)
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INSN_LSX(vmulwev_h_b, vvv)
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INSN_LSX(vmulwev_w_h, vvv)
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INSN_LSX(vmulwev_d_w, vvv)
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INSN_LSX(vmulwev_q_d, vvv)
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INSN_LSX(vmulwod_h_b, vvv)
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INSN_LSX(vmulwod_w_h, vvv)
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INSN_LSX(vmulwod_d_w, vvv)
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INSN_LSX(vmulwod_q_d, vvv)
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INSN_LSX(vmulwev_h_bu, vvv)
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INSN_LSX(vmulwev_w_hu, vvv)
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INSN_LSX(vmulwev_d_wu, vvv)
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INSN_LSX(vmulwev_q_du, vvv)
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INSN_LSX(vmulwod_h_bu, vvv)
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INSN_LSX(vmulwod_w_hu, vvv)
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INSN_LSX(vmulwod_d_wu, vvv)
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INSN_LSX(vmulwod_q_du, vvv)
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INSN_LSX(vmulwev_h_bu_b, vvv)
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INSN_LSX(vmulwev_w_hu_h, vvv)
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INSN_LSX(vmulwev_d_wu_w, vvv)
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INSN_LSX(vmulwev_q_du_d, vvv)
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INSN_LSX(vmulwod_h_bu_b, vvv)
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INSN_LSX(vmulwod_w_hu_h, vvv)
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INSN_LSX(vmulwod_d_wu_w, vvv)
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INSN_LSX(vmulwod_q_du_d, vvv)
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INSN_LSX(vmadd_b, vvv)
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INSN_LSX(vmadd_h, vvv)
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INSN_LSX(vmadd_w, vvv)
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INSN_LSX(vmadd_d, vvv)
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INSN_LSX(vmsub_b, vvv)
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INSN_LSX(vmsub_h, vvv)
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INSN_LSX(vmsub_w, vvv)
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INSN_LSX(vmsub_d, vvv)
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INSN_LSX(vmaddwev_h_b, vvv)
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INSN_LSX(vmaddwev_w_h, vvv)
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INSN_LSX(vmaddwev_d_w, vvv)
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INSN_LSX(vmaddwev_q_d, vvv)
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INSN_LSX(vmaddwod_h_b, vvv)
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INSN_LSX(vmaddwod_w_h, vvv)
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INSN_LSX(vmaddwod_d_w, vvv)
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INSN_LSX(vmaddwod_q_d, vvv)
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INSN_LSX(vmaddwev_h_bu, vvv)
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INSN_LSX(vmaddwev_w_hu, vvv)
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INSN_LSX(vmaddwev_d_wu, vvv)
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INSN_LSX(vmaddwev_q_du, vvv)
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INSN_LSX(vmaddwod_h_bu, vvv)
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INSN_LSX(vmaddwod_w_hu, vvv)
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INSN_LSX(vmaddwod_d_wu, vvv)
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INSN_LSX(vmaddwod_q_du, vvv)
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INSN_LSX(vmaddwev_h_bu_b, vvv)
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INSN_LSX(vmaddwev_w_hu_h, vvv)
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INSN_LSX(vmaddwev_d_wu_w, vvv)
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INSN_LSX(vmaddwev_q_du_d, vvv)
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INSN_LSX(vmaddwod_h_bu_b, vvv)
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INSN_LSX(vmaddwod_w_hu_h, vvv)
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INSN_LSX(vmaddwod_d_wu_w, vvv)
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INSN_LSX(vmaddwod_q_du_d, vvv)
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INSN_LSX(vdiv_b, vvv)
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INSN_LSX(vdiv_h, vvv)
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INSN_LSX(vdiv_w, vvv)
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INSN_LSX(vdiv_d, vvv)
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INSN_LSX(vdiv_bu, vvv)
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INSN_LSX(vdiv_hu, vvv)
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INSN_LSX(vdiv_wu, vvv)
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INSN_LSX(vdiv_du, vvv)
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INSN_LSX(vmod_b, vvv)
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INSN_LSX(vmod_h, vvv)
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INSN_LSX(vmod_w, vvv)
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INSN_LSX(vmod_d, vvv)
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INSN_LSX(vmod_bu, vvv)
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INSN_LSX(vmod_hu, vvv)
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INSN_LSX(vmod_wu, vvv)
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INSN_LSX(vmod_du, vvv)
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INSN_LSX(vsat_b, vv_i)
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INSN_LSX(vsat_h, vv_i)
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INSN_LSX(vsat_w, vv_i)
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INSN_LSX(vsat_d, vv_i)
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INSN_LSX(vsat_bu, vv_i)
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INSN_LSX(vsat_hu, vv_i)
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INSN_LSX(vsat_wu, vv_i)
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INSN_LSX(vsat_du, vv_i)
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INSN_LSX(vexth_h_b, vv)
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INSN_LSX(vexth_w_h, vv)
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INSN_LSX(vexth_d_w, vv)
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INSN_LSX(vexth_q_d, vv)
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INSN_LSX(vexth_hu_bu, vv)
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INSN_LSX(vexth_wu_hu, vv)
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INSN_LSX(vexth_du_wu, vv)
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INSN_LSX(vexth_qu_du, vv)
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INSN_LSX(vsigncov_b, vvv)
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INSN_LSX(vsigncov_h, vvv)
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INSN_LSX(vsigncov_w, vvv)
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INSN_LSX(vsigncov_d, vvv)
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INSN_LSX(vmskltz_b, vv)
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INSN_LSX(vmskltz_h, vv)
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INSN_LSX(vmskltz_w, vv)
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INSN_LSX(vmskltz_d, vv)
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INSN_LSX(vmskgez_b, vv)
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INSN_LSX(vmsknz_b, vv)
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