61f3c91a67
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. This patch contains all the files, whose maintainer I could not get from ‘get_maintainer.pl’ script. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023124424.20177-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [thuth: Adapted exec.c and qdev-monitor.c to new location] Signed-off-by: Thomas Huth <thuth@redhat.com>
216 lines
6.8 KiB
C
216 lines
6.8 KiB
C
/*
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* QEMU SPAPR PCI BUS definitions
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*
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* Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PCI_HOST_SPAPR_H
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#define PCI_HOST_SPAPR_H
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#include "hw/ppc/spapr.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/xics.h"
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#include "qom/object.h"
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#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
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OBJECT_DECLARE_SIMPLE_TYPE(SpaprPhbState, SPAPR_PCI_HOST_BRIDGE)
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#define SPAPR_PCI_DMA_MAX_WINDOWS 2
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typedef struct SpaprPciMsi {
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uint32_t first_irq;
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uint32_t num;
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} SpaprPciMsi;
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typedef struct SpaprPciMsiMig {
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uint32_t key;
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SpaprPciMsi value;
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} SpaprPciMsiMig;
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typedef struct SpaprPciLsi {
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uint32_t irq;
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} SpaprPciLsi;
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typedef struct SpaprPhbPciNvGpuConfig SpaprPhbPciNvGpuConfig;
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struct SpaprPhbState {
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PCIHostState parent_obj;
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uint32_t index;
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uint64_t buid;
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char *dtbusname;
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bool dr_enabled;
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MemoryRegion memspace, iospace;
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hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size;
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uint64_t mem64_win_pciaddr;
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hwaddr io_win_addr, io_win_size;
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MemoryRegion mem32window, mem64window, iowindow, msiwindow;
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uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS];
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hwaddr dma_win_addr, dma_win_size;
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AddressSpace iommu_as;
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MemoryRegion iommu_root;
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SpaprPciLsi lsi_table[PCI_NUM_PINS];
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GHashTable *msi;
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/* Temporary cache for migration purposes */
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int32_t msi_devs_num;
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SpaprPciMsiMig *msi_devs;
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QLIST_ENTRY(SpaprPhbState) list;
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bool ddw_enabled;
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uint64_t page_size_mask;
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uint64_t dma64_win_addr;
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uint32_t numa_node;
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bool pcie_ecs; /* Allow access to PCIe extended config space? */
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/* Fields for migration compatibility hacks */
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bool pre_2_8_migration;
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uint32_t mig_liobn;
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hwaddr mig_mem_win_addr, mig_mem_win_size;
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hwaddr mig_io_win_addr, mig_io_win_size;
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hwaddr nv2_gpa_win_addr;
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hwaddr nv2_atsd_win_addr;
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SpaprPhbPciNvGpuConfig *nvgpus;
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bool pre_5_1_assoc;
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};
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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#define SPAPR_PCI_MEM32_WIN_SIZE \
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((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
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#define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL /* 1 TiB */
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/* All PCI outbound windows will be within this range */
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#define SPAPR_PCI_BASE (1ULL << 45) /* 32 TiB */
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#define SPAPR_PCI_LIMIT (1ULL << 46) /* 64 TiB */
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#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
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SPAPR_PCI_MEM64_WIN_SIZE - 1)
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#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
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#define SPAPR_PCI_NV2RAM64_WIN_BASE SPAPR_PCI_LIMIT
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#define SPAPR_PCI_NV2RAM64_WIN_SIZE (2 * TiB) /* For up to 6 GPUs 256GB each */
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/* Max number of these GPUsper a physical box */
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#define NVGPU_MAX_NUM 6
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/* Max number of NVLinks per GPU in any physical box */
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#define NVGPU_MAX_LINKS 3
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/*
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* GPU RAM starts at 64TiB so huge DMA window to cover it all ends at 128TiB
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* which is enough. We do not need DMA for ATSD so we put them at 128TiB.
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*/
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#define SPAPR_PCI_NV2ATSD_WIN_BASE (128 * TiB)
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#define SPAPR_PCI_NV2ATSD_WIN_SIZE (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \
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64 * KiB)
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int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb,
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uint32_t intc_phandle, void *fdt, int *node_offset);
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void spapr_pci_rtas_init(void);
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SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid);
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PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
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uint32_t config_addr);
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/* DRC callbacks */
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void spapr_phb_remove_pci_device_cb(DeviceState *dev);
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int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
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void *fdt, int *fdt_start_offset, Error **errp);
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/* VFIO EEH hooks */
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#ifdef CONFIG_LINUX
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bool spapr_phb_eeh_available(SpaprPhbState *sphb);
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int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
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unsigned int addr, int option);
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int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state);
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int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option);
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int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb);
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void spapr_phb_vfio_reset(DeviceState *qdev);
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void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp);
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void spapr_phb_nvgpu_free(SpaprPhbState *sphb);
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void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off,
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Error **errp);
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void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt);
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void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
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SpaprPhbState *sphb);
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#else
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static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb)
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{
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return false;
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}
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static inline int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
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unsigned int addr, int option)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb,
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int *state)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline void spapr_phb_vfio_reset(DeviceState *qdev)
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{
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}
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static inline void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp)
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{
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}
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static inline void spapr_phb_nvgpu_free(SpaprPhbState *sphb)
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{
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}
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static inline void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt,
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int bus_off, Error **errp)
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{
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}
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static inline void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb,
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void *fdt)
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{
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}
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static inline void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt,
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int offset,
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SpaprPhbState *sphb)
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{
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}
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#endif
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void spapr_phb_dma_reset(SpaprPhbState *sphb);
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static inline unsigned spapr_phb_windows_supported(SpaprPhbState *sphb)
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{
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return sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1;
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}
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#endif /* PCI_HOST_SPAPR_H */
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