988f244297
This patch implements a 32 half word FIFO as per imx serial device specifications. If a non empty FIFO is below the trigger level, an ageing timer will tick for a duration of 8 characters. On expiry, AGTIM will be set triggering an interrupt. AGTIM timer resets when there is activity in the receive FIFO. Otherwise, RRDY is set when trigger level is exceeded. The receive trigger level is 8 in newer kernel versions and 1 in older ones. This change will break migration compatibility for the imx boards. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240125151931.83494-1-rayhan.faizel@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: commit message tidyups] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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avr_usart.h | ||
bcm2835_aux.h | ||
cadence_uart.h | ||
cmsdk-apb-uart.h | ||
digic-uart.h | ||
escc.h | ||
goldfish_tty.h | ||
ibex_uart.h | ||
imx_serial.h | ||
mchp_pfsoc_mmuart.h | ||
nrf51_uart.h | ||
parallel-isa.h | ||
parallel.h | ||
pl011.h | ||
renesas_sci.h | ||
riscv_htif.h | ||
serial.h | ||
shakti_uart.h | ||
sifive_uart.h | ||
stm32f2xx_usart.h | ||
xilinx_uartlite.h |