7729e1f4b3
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
53 lines
1.6 KiB
C
53 lines
1.6 KiB
C
/*
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* Xilinx Zynq MPSoC emulation
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*
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* Copyright (C) 2015 Xilinx Inc
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef XLNX_ZYNQMP_H
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#include "qemu-common.h"
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#include "hw/arm/arm.h"
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#include "hw/intc/arm_gic.h"
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#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
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#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
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TYPE_XLNX_ZYNQMP)
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#define XLNX_ZYNQMP_NUM_CPUS 4
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#define XLNX_ZYNQMP_GIC_REGIONS 2
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/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
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* and under-decodes the 64k region. This mirrors the 4k regions to every 4k
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* aligned address in the 64k region. To implement each GIC region needs a
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* number of memory region aliases.
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*/
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#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x4000
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#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
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typedef struct XlnxZynqMPState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
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GICState gic;
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MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
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} XlnxZynqMPState;
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#define XLNX_ZYNQMP_H
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#endif
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