qemu/include/hw/intc
Sai Pavan Boddu 11411489da arm_gic: Mask the un-supported priority bits
The GICv2 allows the implementation to implement a variable number
of priority bits; unimplemented bits in the priority registers
are read as zeros, writes ignored. We were previously always
implementing a full 8 bits of priority, which is allowed but not
what the real hardware typically does (which is usually to have
4 or 5 bits of priority).

Add a new device property to allow the number of implemented
property bits to be specified.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: improved commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28 16:14:57 +00:00
..
allwinner-a10-pic.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
arm_gic_common.h arm_gic: Mask the un-supported priority bits 2020-02-28 16:14:57 +00:00
arm_gic.h arm_gic: Mask the un-supported priority bits 2020-02-28 16:14:57 +00:00
arm_gicv3_common.h
arm_gicv3_its_common.h
arm_gicv3.h
armv7m_nvic.h
aspeed_vic.h
bcm2835_ic.h
bcm2836_control.h
heathrow_pic.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
i8259.h hw: replace hw/i386/pc.h with a header just for the i8259 2019-12-17 19:33:49 +01:00
imx_avic.h
imx_gpcv2.h
intc.h
mips_gic.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
realview_gic.h
xlnx-pmu-iomod-intc.h Clean up header guards that don't match their file name 2019-05-13 08:58:55 +02:00
xlnx-zynqmp-ipi.h