141 lines
4.1 KiB
C
141 lines
4.1 KiB
C
/*
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* AST2400 SoC
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*
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* Andrew Jeffery <andrew@aj.id.au>
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* Jeremy Kerr <jk@ozlabs.org>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/address-spaces.h"
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#include "hw/arm/ast2400.h"
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#include "hw/char/serial.h"
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#define AST2400_UART_5_BASE 0x00184000
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#define AST2400_IOMEM_SIZE 0x00200000
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#define AST2400_IOMEM_BASE 0x1E600000
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#define AST2400_VIC_BASE 0x1E6C0000
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#define AST2400_TIMER_BASE 0x1E782000
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static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
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static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
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/*
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* IO handlers: simply catch any reads/writes to IO addresses that aren't
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* handled by a device mapping.
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*/
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static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
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__func__, offset, size);
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return 0;
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}
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static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
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__func__, offset, value, size);
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}
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static const MemoryRegionOps ast2400_io_ops = {
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.read = ast2400_io_read,
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.write = ast2400_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void ast2400_init(Object *obj)
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{
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AST2400State *s = AST2400(obj);
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s->cpu = cpu_arm_init("arm926");
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object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
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object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
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qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
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object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
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object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
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qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
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}
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static void ast2400_realize(DeviceState *dev, Error **errp)
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{
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int i;
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AST2400State *s = AST2400(dev);
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Error *err = NULL;
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/* IO space */
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memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL,
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"ast2400.io", AST2400_IOMEM_SIZE);
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memory_region_add_subregion_overlap(get_system_memory(), AST2400_IOMEM_BASE,
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&s->iomem, -1);
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/* VIC */
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object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
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qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
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qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
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/* Timer */
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object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, AST2400_TIMER_BASE);
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for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
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qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
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}
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/* UART - attach an 8250 to the IO space as our UART5 */
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if (serial_hds[0]) {
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qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
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serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2,
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uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
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}
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}
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static void ast2400_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = ast2400_realize;
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/*
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* Reason: creates an ARM CPU, thus use after free(), see
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* arm_cpu_class_init()
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*/
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dc->cannot_destroy_with_object_finalize_yet = true;
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}
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static const TypeInfo ast2400_type_info = {
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.name = TYPE_AST2400,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AST2400State),
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.instance_init = ast2400_init,
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.class_init = ast2400_class_init,
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};
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static void ast2400_register_types(void)
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{
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type_register_static(&ast2400_type_info);
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}
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type_init(ast2400_register_types)
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