76dbd28935
Fairly easy, just load from to gprs into a single vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
522 lines
15 KiB
C
522 lines
15 KiB
C
/*
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* QEMU TCG support -- s390x vector instruction translation functions
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*
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* Copyright (C) 2019 Red Hat Inc
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*
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* Authors:
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* David Hildenbrand <david@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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/*
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* For most instructions that use the same element size for reads and
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* writes, we can use real gvec vector expansion, which potantially uses
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* real host vector instructions. As they only work up to 64 bit elements,
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* 128 bit elements (vector is a single element) have to be handled
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* differently. Operations that are too complicated to encode via TCG ops
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* are handled via gvec ool (out-of-line) handlers.
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*
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* As soon as instructions use different element sizes for reads and writes
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* or access elements "out of their element scope" we expand them manually
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* in fancy loops, as gvec expansion does not deal with actual element
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* numbers and does also not support access to other elements.
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*
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* 128 bit elements:
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* As we only have i32/i64, such elements have to be loaded into two
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* i64 values and can then be processed e.g. by tcg_gen_add2_i64.
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*
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* Sizes:
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* On s390x, the operand size (oprsz) and the maximum size (maxsz) are
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* always 16 (128 bit). What gvec code calls "vece", s390x calls "es",
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* a.k.a. "element size". These values nicely map to MO_8 ... MO_64. Only
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* 128 bit element size has to be treated in a special way (MO_64 + 1).
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* We will use ES_* instead of MO_* for this reason in this file.
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*
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* CC handling:
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* As gvec ool-helpers can currently not return values (besides via
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* pointers like vectors or cpu_env), whenever we have to set the CC and
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* can't conclude the value from the result vector, we will directly
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* set it in "env->cc_op" and mark it as static via set_cc_static()".
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* Whenever this is done, the helper writes globals (cc_op).
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*/
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#define NUM_VEC_ELEMENT_BYTES(es) (1 << (es))
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#define NUM_VEC_ELEMENTS(es) (16 / NUM_VEC_ELEMENT_BYTES(es))
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#define NUM_VEC_ELEMENT_BITS(es) (NUM_VEC_ELEMENT_BYTES(es) * BITS_PER_BYTE)
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#define ES_8 MO_8
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#define ES_16 MO_16
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#define ES_32 MO_32
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#define ES_64 MO_64
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#define ES_128 4
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static inline bool valid_vec_element(uint8_t enr, TCGMemOp es)
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{
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return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1));
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}
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static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
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TCGMemOp memop)
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{
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const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
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switch (memop) {
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case ES_8:
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tcg_gen_ld8u_i64(dst, cpu_env, offs);
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break;
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case ES_16:
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tcg_gen_ld16u_i64(dst, cpu_env, offs);
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break;
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case ES_32:
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tcg_gen_ld32u_i64(dst, cpu_env, offs);
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break;
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case ES_8 | MO_SIGN:
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tcg_gen_ld8s_i64(dst, cpu_env, offs);
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break;
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case ES_16 | MO_SIGN:
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tcg_gen_ld16s_i64(dst, cpu_env, offs);
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break;
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case ES_32 | MO_SIGN:
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tcg_gen_ld32s_i64(dst, cpu_env, offs);
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break;
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case ES_64:
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case ES_64 | MO_SIGN:
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tcg_gen_ld_i64(dst, cpu_env, offs);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
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TCGMemOp memop)
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{
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const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
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switch (memop) {
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case ES_8:
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tcg_gen_st8_i64(src, cpu_env, offs);
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break;
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case ES_16:
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tcg_gen_st16_i64(src, cpu_env, offs);
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break;
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case ES_32:
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tcg_gen_st32_i64(src, cpu_env, offs);
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break;
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case ES_64:
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tcg_gen_st_i64(src, cpu_env, offs);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
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uint8_t es)
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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/* mask off invalid parts from the element nr */
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tcg_gen_andi_i64(tmp, enr, NUM_VEC_ELEMENTS(es) - 1);
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/* convert it to an element offset relative to cpu_env (vec_reg_offset() */
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tcg_gen_shli_i64(tmp, tmp, es);
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#ifndef HOST_WORDS_BIGENDIAN
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tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es));
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#endif
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tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg));
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/* generate the final ptr by adding cpu_env */
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tcg_gen_trunc_i64_ptr(ptr, tmp);
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tcg_gen_add_ptr(ptr, ptr, cpu_env);
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tcg_temp_free_i64(tmp);
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}
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#define gen_gvec_dup_i64(es, v1, c) \
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tcg_gen_gvec_dup_i64(es, vec_full_reg_offset(v1), 16, 16, c)
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#define gen_gvec_mov(v1, v2) \
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tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \
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16)
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#define gen_gvec_dup64i(v1, c) \
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tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
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static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
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{
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switch (es) {
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case ES_8:
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tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, c);
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break;
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case ES_16:
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tcg_gen_gvec_dup16i(vec_full_reg_offset(reg), 16, 16, c);
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break;
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case ES_32:
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tcg_gen_gvec_dup32i(vec_full_reg_offset(reg), 16, 16, c);
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break;
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case ES_64:
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gen_gvec_dup64i(reg, c);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void zero_vec(uint8_t reg)
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{
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tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0);
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}
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static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
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{
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const uint8_t es = s->insn->data;
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const uint8_t enr = get_field(s->fields, m3);
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TCGv_i64 tmp;
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if (!valid_vec_element(enr, es)) {
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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tmp = tcg_temp_new_i64();
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read_vec_element_i64(tmp, get_field(s->fields, v2), enr, es);
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tcg_gen_add_i64(o->addr1, o->addr1, tmp);
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gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0);
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tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
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write_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
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tcg_temp_free_i64(tmp);
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return DISAS_NEXT;
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}
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static uint64_t generate_byte_mask(uint8_t mask)
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{
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uint64_t r = 0;
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int i;
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for (i = 0; i < 8; i++) {
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if ((mask >> i) & 1) {
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r |= 0xffull << (i * 8);
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}
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}
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return r;
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}
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static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
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{
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const uint16_t i2 = get_field(s->fields, i2);
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if (i2 == (i2 & 0xff) * 0x0101) {
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/*
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* Masks for both 64 bit elements of the vector are the same.
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* Trust tcg to produce a good constant loading.
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*/
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gen_gvec_dup64i(get_field(s->fields, v1),
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generate_byte_mask(i2 & 0xff));
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} else {
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_movi_i64(t, generate_byte_mask(i2 >> 8));
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write_vec_element_i64(t, get_field(s->fields, v1), 0, ES_64);
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tcg_gen_movi_i64(t, generate_byte_mask(i2));
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write_vec_element_i64(t, get_field(s->fields, v1), 1, ES_64);
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tcg_temp_free_i64(t);
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}
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return DISAS_NEXT;
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}
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static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
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{
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const uint8_t es = get_field(s->fields, m4);
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const uint8_t bits = NUM_VEC_ELEMENT_BITS(es);
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const uint8_t i2 = get_field(s->fields, i2) & (bits - 1);
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const uint8_t i3 = get_field(s->fields, i3) & (bits - 1);
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uint64_t mask = 0;
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int i;
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if (es > ES_64) {
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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/* generate the mask - take care of wrapping */
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for (i = i2; ; i = (i + 1) % bits) {
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mask |= 1ull << (bits - i - 1);
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if (i == i3) {
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break;
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}
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}
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gen_gvec_dupi(es, get_field(s->fields, v1), mask);
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return DISAS_NEXT;
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}
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static DisasJumpType op_vl(DisasContext *s, DisasOps *o)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEQ);
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gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
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tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
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write_vec_element_i64(t0, get_field(s->fields, v1), 0, ES_64);
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write_vec_element_i64(t1, get_field(s->fields, v1), 1, ES_64);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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return DISAS_NEXT;
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}
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static DisasJumpType op_vlr(DisasContext *s, DisasOps *o)
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{
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gen_gvec_mov(get_field(s->fields, v1), get_field(s->fields, v2));
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return DISAS_NEXT;
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}
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static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o)
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{
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const uint8_t es = get_field(s->fields, m3);
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TCGv_i64 tmp;
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if (es > ES_64) {
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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tmp = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
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gen_gvec_dup_i64(es, get_field(s->fields, v1), tmp);
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tcg_temp_free_i64(tmp);
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return DISAS_NEXT;
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}
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static DisasJumpType op_vle(DisasContext *s, DisasOps *o)
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{
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const uint8_t es = s->insn->data;
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const uint8_t enr = get_field(s->fields, m3);
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TCGv_i64 tmp;
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if (!valid_vec_element(enr, es)) {
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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tmp = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
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write_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
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tcg_temp_free_i64(tmp);
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return DISAS_NEXT;
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}
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static DisasJumpType op_vlei(DisasContext *s, DisasOps *o)
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{
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const uint8_t es = s->insn->data;
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const uint8_t enr = get_field(s->fields, m3);
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TCGv_i64 tmp;
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if (!valid_vec_element(enr, es)) {
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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tmp = tcg_const_i64((int16_t)get_field(s->fields, i2));
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write_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
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tcg_temp_free_i64(tmp);
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return DISAS_NEXT;
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}
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static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o)
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{
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const uint8_t es = get_field(s->fields, m4);
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TCGv_ptr ptr;
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if (es > ES_64) {
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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/* fast path if we don't need the register content */
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if (!get_field(s->fields, b2)) {
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uint8_t enr = get_field(s->fields, d2) & (NUM_VEC_ELEMENTS(es) - 1);
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read_vec_element_i64(o->out, get_field(s->fields, v3), enr, es);
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return DISAS_NEXT;
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}
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ptr = tcg_temp_new_ptr();
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get_vec_element_ptr_i64(ptr, get_field(s->fields, v3), o->addr1, es);
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switch (es) {
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case ES_8:
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tcg_gen_ld8u_i64(o->out, ptr, 0);
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break;
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case ES_16:
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tcg_gen_ld16u_i64(o->out, ptr, 0);
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break;
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case ES_32:
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tcg_gen_ld32u_i64(o->out, ptr, 0);
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break;
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case ES_64:
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tcg_gen_ld_i64(o->out, ptr, 0);
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break;
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default:
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g_assert_not_reached();
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}
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tcg_temp_free_ptr(ptr);
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return DISAS_NEXT;
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}
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static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
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{
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uint8_t es = get_field(s->fields, m3);
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uint8_t enr;
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TCGv_i64 t;
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switch (es) {
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/* rightmost sub-element of leftmost doubleword */
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case ES_8:
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enr = 7;
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break;
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case ES_16:
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enr = 3;
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break;
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case ES_32:
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enr = 1;
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break;
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case ES_64:
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enr = 0;
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break;
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/* leftmost sub-element of leftmost doubleword */
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case 6:
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if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
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es = ES_32;
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enr = 0;
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break;
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}
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default:
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/* fallthrough */
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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t = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
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zero_vec(get_field(s->fields, v1));
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write_vec_element_i64(t, get_field(s->fields, v1), enr, es);
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tcg_temp_free_i64(t);
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return DISAS_NEXT;
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}
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static DisasJumpType op_vlm(DisasContext *s, DisasOps *o)
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{
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const uint8_t v3 = get_field(s->fields, v3);
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uint8_t v1 = get_field(s->fields, v1);
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TCGv_i64 t0, t1;
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if (v3 < v1 || (v3 - v1 + 1) > 16) {
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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/*
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* Check for possible access exceptions by trying to load the last
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* element. The first element will be checked first next.
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*/
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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gen_addi_and_wrap_i64(s, t0, o->addr1, (v3 - v1) * 16 + 8);
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tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_TEQ);
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for (;; v1++) {
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tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
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write_vec_element_i64(t1, v1, 0, ES_64);
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if (v1 == v3) {
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break;
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}
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gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
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tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
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write_vec_element_i64(t1, v1, 1, ES_64);
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gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
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}
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/* Store the last element, loaded first */
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write_vec_element_i64(t0, v1, 1, ES_64);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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return DISAS_NEXT;
|
|
}
|
|
|
|
static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o)
|
|
{
|
|
const int64_t block_size = (1ull << (get_field(s->fields, m3) + 6));
|
|
const int v1_offs = vec_full_reg_offset(get_field(s->fields, v1));
|
|
TCGv_ptr a0;
|
|
TCGv_i64 bytes;
|
|
|
|
if (get_field(s->fields, m3) > 6) {
|
|
gen_program_exception(s, PGM_SPECIFICATION);
|
|
return DISAS_NORETURN;
|
|
}
|
|
|
|
bytes = tcg_temp_new_i64();
|
|
a0 = tcg_temp_new_ptr();
|
|
/* calculate the number of bytes until the next block boundary */
|
|
tcg_gen_ori_i64(bytes, o->addr1, -block_size);
|
|
tcg_gen_neg_i64(bytes, bytes);
|
|
|
|
tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
|
|
gen_helper_vll(cpu_env, a0, o->addr1, bytes);
|
|
tcg_temp_free_i64(bytes);
|
|
tcg_temp_free_ptr(a0);
|
|
return DISAS_NEXT;
|
|
}
|
|
|
|
static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o)
|
|
{
|
|
const uint8_t es = get_field(s->fields, m4);
|
|
TCGv_ptr ptr;
|
|
|
|
if (es > ES_64) {
|
|
gen_program_exception(s, PGM_SPECIFICATION);
|
|
return DISAS_NORETURN;
|
|
}
|
|
|
|
/* fast path if we don't need the register content */
|
|
if (!get_field(s->fields, b2)) {
|
|
uint8_t enr = get_field(s->fields, d2) & (NUM_VEC_ELEMENTS(es) - 1);
|
|
|
|
write_vec_element_i64(o->in2, get_field(s->fields, v1), enr, es);
|
|
return DISAS_NEXT;
|
|
}
|
|
|
|
ptr = tcg_temp_new_ptr();
|
|
get_vec_element_ptr_i64(ptr, get_field(s->fields, v1), o->addr1, es);
|
|
switch (es) {
|
|
case ES_8:
|
|
tcg_gen_st8_i64(o->in2, ptr, 0);
|
|
break;
|
|
case ES_16:
|
|
tcg_gen_st16_i64(o->in2, ptr, 0);
|
|
break;
|
|
case ES_32:
|
|
tcg_gen_st32_i64(o->in2, ptr, 0);
|
|
break;
|
|
case ES_64:
|
|
tcg_gen_st_i64(o->in2, ptr, 0);
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
tcg_temp_free_ptr(ptr);
|
|
|
|
return DISAS_NEXT;
|
|
}
|
|
|
|
static DisasJumpType op_vlvgp(DisasContext *s, DisasOps *o)
|
|
{
|
|
write_vec_element_i64(o->in1, get_field(s->fields, v1), 0, ES_64);
|
|
write_vec_element_i64(o->in2, get_field(s->fields, v1), 1, ES_64);
|
|
return DISAS_NEXT;
|
|
}
|