820613b1c1
s390_cpu_virt_mem_rw() must always return, so callers can react on an exception (e.g. see ioinst_handle_stcrw()). Therefore, using program_interrupt() is wrong. Fix that up. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
562 lines
18 KiB
C
562 lines
18 KiB
C
/*
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* S390x MMU related functions
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*
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* Copyright (c) 2011 Alexander Graf
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* Copyright (c) 2015 Thomas Huth, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "exec/address-spaces.h"
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#include "cpu.h"
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#include "internal.h"
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#include "kvm_s390x.h"
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#include "sysemu/kvm.h"
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#include "exec/exec-all.h"
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#include "trace.h"
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#include "hw/s390x/storage-keys.h"
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/* #define DEBUG_S390 */
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/* #define DEBUG_S390_PTE */
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/* #define DEBUG_S390_STDOUT */
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#ifdef DEBUG_S390
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#ifdef DEBUG_S390_STDOUT
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); \
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if (qemu_log_separate()) qemu_log(fmt, ##__VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
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#endif
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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#ifdef DEBUG_S390_PTE
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#define PTE_DPRINTF DPRINTF
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#else
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#define PTE_DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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/* Fetch/store bits in the translation exception code: */
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#define FS_READ 0x800
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#define FS_WRITE 0x400
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static void trigger_access_exception(CPUS390XState *env, uint32_t type,
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uint32_t ilen, uint64_t tec)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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if (kvm_enabled()) {
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kvm_s390_access_exception(cpu, type, tec);
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} else {
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CPUState *cs = CPU(cpu);
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if (type != PGM_ADDRESSING) {
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stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
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}
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trigger_pgm_exception(env, type, ilen);
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}
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}
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static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, int rw, bool exc)
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{
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uint64_t tec;
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tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46;
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DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
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if (!exc) {
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return;
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}
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trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec);
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}
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static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
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uint32_t type, uint64_t asc, int rw, bool exc)
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{
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int ilen = ILEN_AUTO;
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uint64_t tec;
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tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46;
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DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
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if (!exc) {
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return;
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}
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/* Code accesses have an undefined ilc. */
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if (rw == MMU_INST_FETCH) {
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ilen = 2;
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}
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trigger_access_exception(env, type, ilen, tec);
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}
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/* check whether the address would be proteted by Low-Address Protection */
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static bool is_low_address(uint64_t addr)
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{
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return addr <= 511 || (addr >= 4096 && addr <= 4607);
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}
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/* check whether Low-Address Protection is enabled for mmu_translate() */
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static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc)
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{
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if (!(env->cregs[0] & CR0_LOWPROT)) {
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return false;
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}
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if (!(env->psw.mask & PSW_MASK_DAT)) {
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return true;
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}
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/* Check the private-space control bit */
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switch (asc) {
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case PSW_ASC_PRIMARY:
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return !(env->cregs[1] & _ASCE_PRIVATE_SPACE);
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case PSW_ASC_SECONDARY:
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return !(env->cregs[7] & _ASCE_PRIVATE_SPACE);
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case PSW_ASC_HOME:
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return !(env->cregs[13] & _ASCE_PRIVATE_SPACE);
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default:
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/* We don't support access register mode */
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error_report("unsupported addressing mode");
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exit(1);
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}
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}
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/**
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* Translate real address to absolute (= physical)
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* address by taking care of the prefix mapping.
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*/
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target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
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{
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if (raddr < 0x2000) {
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return raddr + env->psa; /* Map the lowcore. */
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} else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
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return raddr - env->psa; /* Map the 0 page. */
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}
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return raddr;
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}
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/* Decode page table entry (normal 4KB page) */
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static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t pt_entry,
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target_ulong *raddr, int *flags, int rw, bool exc)
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{
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if (pt_entry & _PAGE_INVALID) {
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DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, pt_entry);
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trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc);
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return -1;
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}
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if (pt_entry & _PAGE_RES0) {
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
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return -1;
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}
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if (pt_entry & _PAGE_RO) {
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*flags &= ~PAGE_WRITE;
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}
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*raddr = pt_entry & _ASCE_ORIGIN;
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PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, pt_entry);
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return 0;
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}
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/* Decode segment table entry */
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static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t st_entry,
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target_ulong *raddr, int *flags, int rw,
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bool exc)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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uint64_t origin, offs, pt_entry;
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if (st_entry & _SEGMENT_ENTRY_RO) {
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*flags &= ~PAGE_WRITE;
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}
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if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
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/* Decode EDAT1 segment frame absolute address (1MB page) */
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*raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);
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PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);
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return 0;
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}
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/* Look up 4KB page entry */
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origin = st_entry & _SEGMENT_ENTRY_ORIGIN;
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offs = (vaddr & VADDR_PX) >> 9;
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pt_entry = ldq_phys(cs->as, origin + offs);
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PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
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__func__, origin, offs, pt_entry);
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return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
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}
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/* Decode region table entries */
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static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t entry, int level,
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target_ulong *raddr, int *flags, int rw,
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bool exc)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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uint64_t origin, offs, new_entry;
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const int pchks[4] = {
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PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
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PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS
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};
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PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry);
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origin = entry & _REGION_ENTRY_ORIGIN;
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offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
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new_entry = ldq_phys(cs->as, origin + offs);
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PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
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__func__, origin, offs, new_entry);
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if ((new_entry & _REGION_ENTRY_INV) != 0) {
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DPRINTF("%s: invalid region\n", __func__);
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trigger_page_fault(env, vaddr, pchks[level / 4], asc, rw, exc);
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return -1;
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}
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if ((new_entry & _REGION_ENTRY_TYPE_MASK) != level) {
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
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return -1;
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}
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if (level == _ASCE_TYPE_SEGMENT) {
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return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
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rw, exc);
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}
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/* Check region table offset and length */
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offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3;
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if (offs < ((new_entry & _REGION_ENTRY_TF) >> 6)
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|| offs > (new_entry & _REGION_ENTRY_LENGTH)) {
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DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry);
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trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc);
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return -1;
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}
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if ((env->cregs[0] & CR0_EDAT) && (new_entry & _REGION_ENTRY_RO)) {
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*flags &= ~PAGE_WRITE;
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}
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/* yet another region */
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return mmu_translate_region(env, vaddr, asc, new_entry, level - 4,
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raddr, flags, rw, exc);
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}
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static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t asce, target_ulong *raddr,
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int *flags, int rw, bool exc)
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{
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int level;
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int r;
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if (asce & _ASCE_REAL_SPACE) {
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/* direct mapping */
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*raddr = vaddr;
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return 0;
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}
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level = asce & _ASCE_TYPE_MASK;
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switch (level) {
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case _ASCE_TYPE_REGION1:
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if ((vaddr >> 62) > (asce & _ASCE_TABLE_LENGTH)) {
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trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, exc);
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return -1;
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}
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break;
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case _ASCE_TYPE_REGION2:
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if (vaddr & 0xffe0000000000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xffe0000000000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
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return -1;
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}
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if ((vaddr >> 51 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
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trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc);
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return -1;
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}
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break;
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case _ASCE_TYPE_REGION3:
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if (vaddr & 0xfffffc0000000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xfffffc0000000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
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return -1;
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}
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if ((vaddr >> 40 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
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trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, exc);
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return -1;
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}
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break;
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case _ASCE_TYPE_SEGMENT:
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if (vaddr & 0xffffffff80000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xffffffff80000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
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return -1;
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}
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if ((vaddr >> 29 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
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trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc);
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return -1;
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}
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break;
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}
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r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
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exc);
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if (rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE)) {
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trigger_prot_fault(env, vaddr, asc, rw, exc);
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return -1;
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}
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return r;
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}
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/**
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* Translate a virtual (logical) address into a physical (absolute) address.
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* @param vaddr the virtual address
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* @param rw 0 = read, 1 = write, 2 = code fetch
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* @param asc address space control (one of the PSW_ASC_* modes)
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* @param raddr the translated address is stored to this pointer
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* @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
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* @param exc true = inject a program check if a fault occurred
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* @return 0 if the translation was successful, -1 if a fault occurred
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*/
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int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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target_ulong *raddr, int *flags, bool exc)
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{
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static S390SKeysState *ss;
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static S390SKeysClass *skeyclass;
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int r = -1;
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uint8_t key;
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if (unlikely(!ss)) {
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ss = s390_get_skeys_device();
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skeyclass = S390_SKEYS_GET_CLASS(ss);
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}
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*flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
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/*
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* If any part of this page is currently protected, make sure the
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* TLB entry will not be reused.
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*
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* As the protected range is always the first 512 bytes of the
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* two first pages, we are able to catch all writes to these areas
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* just by looking at the start address (triggering the tlb miss).
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*/
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*flags |= PAGE_WRITE_INV;
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if (is_low_address(vaddr) && rw == MMU_DATA_STORE) {
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if (exc) {
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trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
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}
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return -EACCES;
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}
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}
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vaddr &= TARGET_PAGE_MASK;
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if (!(env->psw.mask & PSW_MASK_DAT)) {
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*raddr = vaddr;
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r = 0;
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goto out;
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}
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switch (asc) {
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case PSW_ASC_PRIMARY:
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PTE_DPRINTF("%s: asc=primary\n", __func__);
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r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,
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rw, exc);
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break;
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case PSW_ASC_HOME:
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PTE_DPRINTF("%s: asc=home\n", __func__);
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r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,
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rw, exc);
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break;
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case PSW_ASC_SECONDARY:
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PTE_DPRINTF("%s: asc=secondary\n", __func__);
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/*
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* Instruction: Primary
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* Data: Secondary
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*/
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if (rw == MMU_INST_FETCH) {
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r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
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raddr, flags, rw, exc);
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*flags &= ~(PAGE_READ | PAGE_WRITE);
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} else {
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r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],
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raddr, flags, rw, exc);
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*flags &= ~(PAGE_EXEC);
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}
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break;
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case PSW_ASC_ACCREG:
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default:
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hw_error("guest switched to unknown asc mode\n");
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break;
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}
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out:
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/* Convert real address -> absolute address */
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*raddr = mmu_real2abs(env, *raddr);
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if (r == 0 && *raddr < ram_size) {
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if (skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) {
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trace_get_skeys_nonzero(r);
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return 0;
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}
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if (*flags & PAGE_READ) {
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key |= SK_R;
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}
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if (*flags & PAGE_WRITE) {
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key |= SK_C;
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}
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if (skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) {
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trace_set_skeys_nonzero(r);
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return 0;
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}
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}
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return r;
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}
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/**
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* translate_pages: Translate a set of consecutive logical page addresses
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* to absolute addresses. This function is used for TCG and old KVM without
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* the MEMOP interface.
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*/
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static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
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target_ulong *pages, bool is_write)
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{
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uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
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CPUS390XState *env = &cpu->env;
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int ret, i, pflags;
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for (i = 0; i < nr_pages; i++) {
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ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, true);
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if (ret) {
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return ret;
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}
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if (!address_space_access_valid(&address_space_memory, pages[i],
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TARGET_PAGE_SIZE, is_write)) {
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trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
|
|
return -EFAULT;
|
|
}
|
|
addr += TARGET_PAGE_SIZE;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* s390_cpu_virt_mem_rw:
|
|
* @laddr: the logical start address
|
|
* @ar: the access register number
|
|
* @hostbuf: buffer in host memory. NULL = do only checks w/o copying
|
|
* @len: length that should be transferred
|
|
* @is_write: true = write, false = read
|
|
* Returns: 0 on success, non-zero if an exception occurred
|
|
*
|
|
* Copy from/to guest memory using logical addresses. Note that we inject a
|
|
* program interrupt in case there is an error while accessing the memory.
|
|
*
|
|
* This function will always return (also for TCG), make sure to call
|
|
* s390_cpu_virt_mem_handle_exc() to properly exit the CPU loop.
|
|
*/
|
|
int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
|
|
int len, bool is_write)
|
|
{
|
|
int currlen, nr_pages, i;
|
|
target_ulong *pages;
|
|
int ret;
|
|
|
|
if (kvm_enabled()) {
|
|
ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write);
|
|
if (ret >= 0) {
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS)
|
|
+ 1;
|
|
pages = g_malloc(nr_pages * sizeof(*pages));
|
|
|
|
ret = translate_pages(cpu, laddr, nr_pages, pages, is_write);
|
|
if (ret == 0 && hostbuf != NULL) {
|
|
/* Copy data by stepping through the area page by page */
|
|
for (i = 0; i < nr_pages; i++) {
|
|
currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE));
|
|
cpu_physical_memory_rw(pages[i] | (laddr & ~TARGET_PAGE_MASK),
|
|
hostbuf, currlen, is_write);
|
|
laddr += currlen;
|
|
hostbuf += currlen;
|
|
len -= currlen;
|
|
}
|
|
}
|
|
|
|
g_free(pages);
|
|
return ret;
|
|
}
|
|
|
|
void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra)
|
|
{
|
|
/* KVM will handle the interrupt automatically, TCG has to exit the TB */
|
|
#ifdef CONFIG_TCG
|
|
if (tcg_enabled()) {
|
|
cpu_loop_exit_restore(CPU(cpu), ra);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* Translate a real address into a physical (absolute) address.
|
|
* @param raddr the real address
|
|
* @param rw 0 = read, 1 = write, 2 = code fetch
|
|
* @param addr the translated address is stored to this pointer
|
|
* @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
|
|
* @return 0 if the translation was successful, < 0 if a fault occurred
|
|
*/
|
|
int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
|
|
target_ulong *addr, int *flags)
|
|
{
|
|
const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT;
|
|
|
|
*flags = PAGE_READ | PAGE_WRITE;
|
|
if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) {
|
|
/* see comment in mmu_translate() how this works */
|
|
*flags |= PAGE_WRITE_INV;
|
|
if (is_low_address(raddr) && rw == MMU_DATA_STORE) {
|
|
trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
|
|
return -EACCES;
|
|
}
|
|
}
|
|
|
|
*addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK);
|
|
|
|
/* TODO: storage key handling */
|
|
return 0;
|
|
}
|