75fe97b429
Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Invert the #ifdef'ry in TCGCPUOps structure for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-6-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
222 lines
8.1 KiB
C
222 lines
8.1 KiB
C
/*
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* TCG CPU-specific operations
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*
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* Copyright 2021 SUSE LLC
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef TCG_CPU_OPS_H
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#define TCG_CPU_OPS_H
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#include "hw/core/cpu.h"
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struct TCGCPUOps {
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/**
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* @initialize: Initalize TCG state
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*
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* Called when the first CPU is realized.
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*/
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void (*initialize)(void);
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/**
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* @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
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*
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* This is called when we abandon execution of a TB before starting it,
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* and must set all parts of the CPU state which the previous TB in the
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* chain may not have updated.
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* By default, when this is NULL, a call is made to @set_pc(tb->pc).
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*
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* If more state needs to be restored, the target must implement a
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* function to restore all the state, and register it here.
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*/
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void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb);
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/**
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* @restore_state_to_opc: Synchronize state from INDEX_op_start_insn
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*
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* This is called when we unwind state in the middle of a TB,
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* usually before raising an exception. Set all part of the CPU
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* state which are tracked insn-by-insn in the target-specific
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* arguments to start_insn, passed as @data.
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*/
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void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb,
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const uint64_t *data);
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/** @cpu_exec_enter: Callback for cpu_exec preparation */
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void (*cpu_exec_enter)(CPUState *cpu);
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/** @cpu_exec_exit: Callback for cpu_exec cleanup */
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void (*cpu_exec_exit)(CPUState *cpu);
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/** @debug_excp_handler: Callback for handling debug exceptions */
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void (*debug_excp_handler)(CPUState *cpu);
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#ifdef NEED_CPU_H
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#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
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/**
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* @fake_user_interrupt: Callback for 'fake exception' handling.
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*
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* Simulate 'fake exception' which will be handled outside the
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* cpu execution loop (hack for x86 user mode).
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*/
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void (*fake_user_interrupt)(CPUState *cpu);
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#else
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/**
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* @do_interrupt: Callback for interrupt handling.
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*/
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void (*do_interrupt)(CPUState *cpu);
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#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
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#ifdef CONFIG_USER_ONLY
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/**
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* record_sigsegv:
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* @cpu: cpu context
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* @addr: faulting guest address
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* @access_type: access was read/write/execute
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* @maperr: true for invalid page, false for permission fault
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* @ra: host pc for unwinding
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*
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* We are about to raise SIGSEGV with si_code set for @maperr,
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* and si_addr set for @addr. Record anything further needed
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* for the signal ucontext_t.
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*
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* If the emulated kernel does not provide anything to the signal
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* handler with anything besides the user context registers, and
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* the siginfo_t, then this hook need do nothing and may be omitted.
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* Otherwise, record the data and return; the caller will raise
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* the signal, unwind the cpu state, and return to the main loop.
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*
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* If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
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* so that a "normal" cpu exception can be raised. In this case,
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* the signal must be raised by the architecture cpu_loop.
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*/
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void (*record_sigsegv)(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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bool maperr, uintptr_t ra);
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/**
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* record_sigbus:
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* @cpu: cpu context
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* @addr: misaligned guest address
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* @access_type: access was read/write/execute
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* @ra: host pc for unwinding
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*
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* We are about to raise SIGBUS with si_code BUS_ADRALN,
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* and si_addr set for @addr. Record anything further needed
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* for the signal ucontext_t.
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*
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* If the emulated kernel does not provide the signal handler with
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* anything besides the user context registers, and the siginfo_t,
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* then this hook need do nothing and may be omitted.
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* Otherwise, record the data and return; the caller will raise
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* the signal, unwind the cpu state, and return to the main loop.
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*
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* If it is simpler to re-use the sysemu do_unaligned_access code,
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* @ra is provided so that a "normal" cpu exception can be raised.
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* In this case, the signal must be raised by the architecture cpu_loop.
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*/
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void (*record_sigbus)(CPUState *cpu, vaddr addr,
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MMUAccessType access_type, uintptr_t ra);
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#else
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/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
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bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
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/**
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* @tlb_fill: Handle a softmmu tlb miss
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*
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* If the access is valid, call tlb_set_page and return true;
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* if the access is invalid and probe is true, return false;
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* otherwise raise an exception and do not return.
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*/
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bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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/**
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* @do_transaction_failed: Callback for handling failed memory transactions
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* (ie bus faults or external aborts; not MMU faults)
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*/
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void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
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unsigned size, MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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/**
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* @do_unaligned_access: Callback for unaligned access handling
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* The callback must exit via raising an exception.
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*/
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G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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/**
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* @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
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*/
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vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
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/**
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* @debug_check_watchpoint: return true if the architectural
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* watchpoint whose address has matched should really fire, used by ARM
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* and RISC-V
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*/
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bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
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/**
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* @debug_check_breakpoint: return true if the architectural
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* breakpoint whose PC has matched should really fire.
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*/
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bool (*debug_check_breakpoint)(CPUState *cpu);
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/**
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* @io_recompile_replay_branch: Callback for cpu_io_recompile.
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*
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* The cpu has been stopped, and cpu_restore_state_from_tb has been
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* called. If the faulting instruction is in a delay slot, and the
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* target architecture requires re-execution of the branch, then
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* adjust the cpu state as required and return true.
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*/
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bool (*io_recompile_replay_branch)(CPUState *cpu,
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const TranslationBlock *tb);
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#endif /* !CONFIG_USER_ONLY */
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#endif /* NEED_CPU_H */
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};
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
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MemTxAttrs atr, int fl, uintptr_t ra)
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{
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}
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static inline int cpu_watchpoint_address_matches(CPUState *cpu,
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vaddr addr, vaddr len)
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{
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return 0;
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}
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#else
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/**
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* cpu_check_watchpoint:
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* @cpu: cpu context
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* @addr: guest virtual address
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* @len: access length
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* @attrs: memory access attributes
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* @flags: watchpoint access type
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* @ra: unwind return address
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*
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* Check for a watchpoint hit in [addr, addr+len) of the type
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* specified by @flags. Exit via exception with a hit.
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*/
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void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
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MemTxAttrs attrs, int flags, uintptr_t ra);
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/**
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* cpu_watchpoint_address_matches:
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* @cpu: cpu context
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* @addr: guest virtual address
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* @len: access length
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*
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* Return the watchpoint flags that apply to [addr, addr+len).
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* If no watchpoint is registered for the range, the result is 0.
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*/
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int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
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#endif
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#endif /* TCG_CPU_OPS_H */
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