qemu/target/riscv
Palmer Dabbelt fd990e86a7
RISC-V: Add a missing "," in riscv_excp_names
This would almost certainly cause the exception names to be reported
incorrectly.  Coverity found the issue (CID 1420223).  As per Peter's
suggestion, I've also added a comma at the end of the list to avoid the issue
reappearing in the future.

Fixes: ab67a1d07a ("target/riscv: Add support for the new execption numbers")
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-05 12:01:43 -08:00
..
insn_trans
cpu_bits.h
cpu_helper.c
cpu_user.h
cpu-param.h
cpu.c
cpu.h
csr.c
fpu_helper.c
gdbstub.c
helper.h
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h
Makefile.objs
monitor.c
op_helper.c
pmp.c
pmp.h
trace-events
translate.c