ffc672aa97
Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
53 lines
1.3 KiB
Meson
53 lines
1.3 KiB
Meson
gen = [
|
|
decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'),
|
|
decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
|
|
decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
|
|
decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
|
|
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
|
|
]
|
|
|
|
mips_ss = ss.source_set()
|
|
mips_ss.add(files(
|
|
'cpu.c',
|
|
'gdbstub.c',
|
|
))
|
|
mips_tcg_ss = ss.source_set()
|
|
mips_tcg_ss.add(gen)
|
|
mips_tcg_ss.add(files(
|
|
'dsp_helper.c',
|
|
'fpu_helper.c',
|
|
'lmmi_helper.c',
|
|
'msa_helper.c',
|
|
'msa_translate.c',
|
|
'op_helper.c',
|
|
'rel6_translate.c',
|
|
'tlb_helper.c',
|
|
'translate.c',
|
|
'translate_addr_const.c',
|
|
'txx9_translate.c',
|
|
))
|
|
mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files(
|
|
'tx79_translate.c',
|
|
))
|
|
mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files(
|
|
'mxu_translate.c',
|
|
))
|
|
|
|
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
|
|
|
|
mips_softmmu_ss = ss.source_set()
|
|
mips_softmmu_ss.add(files(
|
|
'addr.c',
|
|
'cp0_timer.c',
|
|
'machine.c',
|
|
))
|
|
mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
|
|
'cp0_helper.c',
|
|
'mips-semi.c',
|
|
))
|
|
|
|
mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss])
|
|
|
|
target_arch += {'mips': mips_ss}
|
|
target_softmmu_arch += {'mips': mips_softmmu_ss}
|