Jim Wilson 753e3fe207 RISC-V: Add debug support for accessing CSRs. ... Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function to set it. Disable mode checks when debugger field true. Signed-off-by: Jim Wilson <jimw@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190212230903.9215-1-jimw@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-03-19 05:13:24 -07:00
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alpha	avoid TABs in files that only contain a few	2019-01-11 15:46:56 +01:00
arm	target/arm: Check access permission to ADDVL/ADDPL/RDVL	2019-03-15 11:12:29 +00:00
cris	avoid TABs in files that only contain a few	2019-01-11 15:46:56 +01:00
hppa	target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXIT	2019-03-15 10:09:55 -07:00
i386	i386: extended the cpuid_level when Intel PT is enabled	2019-03-11 16:33:49 +01:00
lm32	tcg-next queue	2018-06-04 11:28:31 +01:00
m68k	target/m68k: Fix LGPL information in the file headers	2019-01-30 14:20:13 +01:00
microblaze	target/microblaze: Add props enabling exceptions on failed bus accesses	2019-01-22 03:17:34 -08:00
mips	target/mips: Preparing for adding MMI instructions	2019-02-27 14:26:14 +01:00
moxie	target/moxie: Fix LGPL information in the file headers	2019-02-06 15:46:11 +01:00
nios2	tcg-next queue	2018-06-04 11:28:31 +01:00
openrisc	target/openrisc: Fix LGPL version number	2019-01-30 11:01:36 +01:00
ppc	spapr: Use CamelCase properly	2019-03-12 14:33:05 +11:00
riscv	RISC-V: Add debug support for accessing CSRs.	2019-03-19 05:13:24 -07:00
s390x	s390x/tcg: Implement VECTOR UNPACK *	2019-03-11 09:31:01 +01:00
sh4	sh4: fix use_icount with linux-user	2018-08-20 00:11:06 +02:00
sparc	qdev-props: remove errp from GlobalProperty	2019-01-07 16:18:42 +04:00
tilegx	avoid TABs in files that only contain a few	2019-01-11 15:46:56 +01:00
tricore	tricore: fixed RCR_CADDN instruction	2019-03-08 10:00:59 +01:00
unicore32	target/unicore32: remove tlb_flush from uc32_init_fn	2018-10-18 18:58:10 -07:00
xtensa	target/xtensa: implement PREFCTL SR	2019-02-28 04:43:22 -08:00