e844f0c5d0
OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState declaration for free. Besides, the QOM code style is to use the structure name as typedef, and QEMU style is to use Camel Case, so rename qemu_or_irq as OrIRQState. Mechanical change using: $ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git grep -l qemu_or_irq) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20230113200138.52869-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
237 lines
8.0 KiB
C
237 lines
8.0 KiB
C
/*
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* ARM SSE (Subsystems for Embedded): IoTKit, SSE-200
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the Arm "Subsystems for Embedded" family of
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* hardware, which include the IoT Kit and the SSE-050, SSE-100 and
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* SSE-200. Currently we model:
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* - the Arm IoT Kit which is documented in
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* https://developer.arm.com/documentation/ecm0601256/latest
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* - the SSE-200 which is documented in
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* https://developer.arm.com/documentation/101104/latest/
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*
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* The IoTKit contains:
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* a Cortex-M33
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* the IDAU
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* some timers and watchdogs
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* two peripheral protection controllers
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* a memory protection controller
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* a security controller
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* a bus fabric which arranges that some parts of the address
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* space are secure and non-secure aliases of each other
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* The SSE-200 additionally contains:
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* a second Cortex-M33
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* two Message Handling Units (MHUs)
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* an optional CryptoCell (which we do not model)
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* more SRAM banks with associated MPCs
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* multiple Power Policy Units (PPUs)
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* a control interface for an icache for each CPU
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* per-CPU identity and control register blocks
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*
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* QEMU interface:
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* + Clock input "MAINCLK": clock for CPUs and most peripherals
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* + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
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* + QOM property "memory" is a MemoryRegion containing the devices provided
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* by the board model.
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* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
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* (In hardware, the SSE-200 permits the number of expansion interrupts
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* for the two CPUs to be configured separately, but we restrict it to
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* being the same for both, to avoid having to have separate Property
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* lists for different variants. This restriction can be relaxed later
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* if necessary.)
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* + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the
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* address of each SRAM bank (and thus the total amount of internal SRAM)
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* + QOM property "init-svtor" sets the initial value of the CPU SVTOR register
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* (where it expects to load the PC and SP from the vector table on reset)
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* + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" which
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* set whether the CPUs have the FPU and DSP features present. The default
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* (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
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* SSE-200 both are present; CPU0 in an SSE-200 has neither.
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* Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
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* + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
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* which are wired to its NVIC lines 32 .. n+32
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* + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
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* CPU 1, which are wired to its NVIC lines 32 .. n+32
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* + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
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* bus master devices in the board model to make transactions into
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* all the devices and memory areas in the IoTKit
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* Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
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* might provide:
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
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* + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
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* Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
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* might provide:
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
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* + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
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* Controlling each of the 16 expansion MPCs which a system using the IoTKit
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* might provide:
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* + named GPIO inputs mpcexp_status[0..15]
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* Controlling each of the 16 expansion MSCs which a system using the IoTKit
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* might provide:
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* + named GPIO inputs mscexp_status[0..15]
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* + named GPIO outputs mscexp_clear[0..15]
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* + named GPIO outputs mscexp_ns[0..15]
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*/
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#ifndef ARMSSE_H
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#define ARMSSE_H
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#include "hw/sysbus.h"
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#include "hw/arm/armv7m.h"
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#include "hw/misc/iotkit-secctl.h"
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#include "hw/misc/tz-ppc.h"
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#include "hw/misc/tz-mpc.h"
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#include "hw/timer/cmsdk-apb-timer.h"
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#include "hw/timer/cmsdk-apb-dualtimer.h"
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#include "hw/timer/sse-counter.h"
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#include "hw/timer/sse-timer.h"
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#include "hw/watchdog/cmsdk-apb-watchdog.h"
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#include "hw/misc/iotkit-sysctl.h"
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#include "hw/misc/iotkit-sysinfo.h"
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#include "hw/misc/armsse-cpuid.h"
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#include "hw/misc/armsse-mhu.h"
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#include "hw/misc/armsse-cpu-pwrctrl.h"
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#include "hw/misc/unimp.h"
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#include "hw/or-irq.h"
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#include "hw/clock.h"
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#include "hw/core/split-irq.h"
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#include "hw/cpu/cluster.h"
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#include "qom/object.h"
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#define TYPE_ARM_SSE "arm-sse"
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OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass,
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ARM_SSE)
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/*
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* These type names are for specific IoTKit subsystems; other than
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* instantiating them, code using these devices should always handle
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* them via the ARMSSE base class, so they have no IOTKIT() etc macros.
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*/
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#define TYPE_IOTKIT "iotkit"
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#define TYPE_SSE200 "sse-200"
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#define TYPE_SSE300 "sse-300"
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/* We have an IRQ splitter and an OR gate input for each external PPC
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* and the 2 internal PPCs
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*/
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#define NUM_INTERNAL_PPCS 2
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#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
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#define NUM_PPCS (NUM_EXTERNAL_PPCS + NUM_INTERNAL_PPCS)
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#define MAX_SRAM_BANKS 4
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#if MAX_SRAM_BANKS > IOTS_NUM_MPC
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#error Too many SRAM banks
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#endif
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#define SSE_MAX_CPUS 2
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#define NUM_PPUS 8
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/* Number of CPU IRQs used by the SSE itself */
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#define NUM_SSE_IRQS 32
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struct ARMSSE {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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ARMv7MState armv7m[SSE_MAX_CPUS];
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CPUClusterState cluster[SSE_MAX_CPUS];
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IoTKitSecCtl secctl;
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TZPPC apb_ppc[NUM_INTERNAL_PPCS];
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TZMPC mpc[IOTS_NUM_MPC];
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CMSDKAPBTimer timer[3];
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OrIRQState ppc_irq_orgate;
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SplitIRQ sec_resp_splitter;
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SplitIRQ ppc_irq_splitter[NUM_PPCS];
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SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
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OrIRQState mpc_irq_orgate;
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OrIRQState nmi_orgate;
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SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS];
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CMSDKAPBDualTimer dualtimer;
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CMSDKAPBWatchdog cmsdk_watchdog[3];
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SSECounter sse_counter;
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SSETimer sse_timer[4];
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IoTKitSysCtl sysctl;
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IoTKitSysCtl sysinfo;
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ARMSSEMHU mhu[2];
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UnimplementedDeviceState unimp[NUM_PPUS];
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UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
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UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
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ARMSSECPUID cpuid[SSE_MAX_CPUS];
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ARMSSECPUPwrCtrl cpu_pwrctrl[SSE_MAX_CPUS];
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/*
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* 'container' holds all devices seen by all CPUs.
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* 'cpu_container[i]' is the view that CPU i has: this has the
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* per-CPU devices of that CPU, plus as the background 'container'
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* (or an alias of it, since we can only use it directly once).
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* container_alias[i] is the alias of 'container' used by CPU i+1;
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* CPU 0 can use 'container' directly.
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*/
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MemoryRegion container;
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MemoryRegion container_alias[SSE_MAX_CPUS - 1];
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MemoryRegion cpu_container[SSE_MAX_CPUS];
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MemoryRegion alias1;
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MemoryRegion alias2;
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MemoryRegion alias3[SSE_MAX_CPUS];
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MemoryRegion sram[MAX_SRAM_BANKS];
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MemoryRegion itcm;
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MemoryRegion dtcm;
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qemu_irq *exp_irqs[SSE_MAX_CPUS];
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qemu_irq ppc0_irq;
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qemu_irq ppc1_irq;
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qemu_irq sec_resp_cfg;
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qemu_irq sec_resp_cfg_in;
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qemu_irq nsc_cfg_in;
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qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
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qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC];
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uint32_t nsccfg;
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Clock *mainclk;
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Clock *s32kclk;
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/* Properties */
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MemoryRegion *board_memory;
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uint32_t exp_numirq;
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uint32_t sram_addr_width;
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uint32_t init_svtor;
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bool cpu_fpu[SSE_MAX_CPUS];
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bool cpu_dsp[SSE_MAX_CPUS];
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};
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typedef struct ARMSSEInfo ARMSSEInfo;
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struct ARMSSEClass {
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SysBusDeviceClass parent_class;
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const ARMSSEInfo *info;
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};
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#endif
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