7309335441
Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
443 lines
14 KiB
C
443 lines
14 KiB
C
/*
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* QEMU sPAPR PCI host originated from Uninorth PCI host
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*
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* Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
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* Copyright (C) 2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "pci_host.h"
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#include "hw/spapr.h"
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#include "hw/spapr_pci.h"
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#include "exec-memory.h"
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#include <libfdt.h>
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#include "hw/pci_internals.h"
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static const uint32_t bars[] = {
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PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1,
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PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3,
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PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5
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/*, PCI_ROM_ADDRESS*/
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};
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static PCIDevice *find_dev(sPAPREnvironment *spapr,
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uint64_t buid, uint32_t config_addr)
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{
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DeviceState *qdev;
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int devfn = (config_addr >> 8) & 0xFF;
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sPAPRPHBState *phb;
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QLIST_FOREACH(phb, &spapr->phbs, list) {
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if (phb->buid != buid) {
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continue;
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}
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QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
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PCIDevice *dev = (PCIDevice *)qdev;
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if (dev->devfn == devfn) {
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return dev;
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}
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}
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}
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return NULL;
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}
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static uint32_t rtas_pci_cfgaddr(uint32_t arg)
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{
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return ((arg >> 20) & 0xf00) | (arg & 0xff);
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}
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static uint32_t rtas_read_pci_config_do(PCIDevice *pci_dev, uint32_t addr,
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uint32_t limit, uint32_t len)
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{
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if ((addr + len) <= limit) {
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return pci_host_config_read_common(pci_dev, addr, limit, len);
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} else {
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return ~0x0;
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}
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}
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static void rtas_write_pci_config_do(PCIDevice *pci_dev, uint32_t addr,
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uint32_t limit, uint32_t val,
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uint32_t len)
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{
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if ((addr + len) <= limit) {
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pci_host_config_write_common(pci_dev, addr, limit, val, len);
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}
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}
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static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
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uint32_t token, uint32_t nargs,
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target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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uint32_t val, size, addr;
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uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
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PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
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if (!dev) {
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rtas_st(rets, 0, -1);
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return;
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}
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size = rtas_ld(args, 3);
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addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
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val = rtas_read_pci_config_do(dev, addr, pci_config_size(dev), size);
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rtas_st(rets, 0, 0);
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rtas_st(rets, 1, val);
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}
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static void rtas_read_pci_config(sPAPREnvironment *spapr,
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uint32_t token, uint32_t nargs,
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target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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uint32_t val, size, addr;
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PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
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if (!dev) {
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rtas_st(rets, 0, -1);
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return;
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}
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size = rtas_ld(args, 1);
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addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
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val = rtas_read_pci_config_do(dev, addr, pci_config_size(dev), size);
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rtas_st(rets, 0, 0);
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rtas_st(rets, 1, val);
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}
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static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
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uint32_t token, uint32_t nargs,
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target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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uint32_t val, size, addr;
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uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
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PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
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if (!dev) {
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rtas_st(rets, 0, -1);
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return;
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}
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val = rtas_ld(args, 4);
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size = rtas_ld(args, 3);
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addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
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rtas_write_pci_config_do(dev, addr, pci_config_size(dev), val, size);
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rtas_st(rets, 0, 0);
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}
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static void rtas_write_pci_config(sPAPREnvironment *spapr,
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uint32_t token, uint32_t nargs,
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target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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uint32_t val, size, addr;
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PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
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if (!dev) {
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rtas_st(rets, 0, -1);
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return;
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}
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val = rtas_ld(args, 2);
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size = rtas_ld(args, 1);
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addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
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rtas_write_pci_config_do(dev, addr, pci_config_size(dev), val, size);
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rtas_st(rets, 0, 0);
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}
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static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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/*
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* Here we need to convert pci_dev + irq_num to some unique value
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* which is less than number of IRQs on the specific bus (now it
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* is 16). At the moment irq_num == device_id (number of the
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* slot?)
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* FIXME: we should swizzle in fn and irq_num
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*/
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return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI;
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}
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static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
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{
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/*
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* Here we use the number returned by pci_spapr_map_irq to find a
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* corresponding qemu_irq.
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*/
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sPAPRPHBState *phb = opaque;
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qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
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}
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static int spapr_phb_init(SysBusDevice *s)
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{
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sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
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int i;
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/* Initialize the LSI table */
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for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
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qemu_irq qirq;
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uint32_t num;
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qirq = spapr_allocate_irq(0, &num);
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if (!qirq) {
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return -1;
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}
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phb->lsi_table[i].dt_irq = num;
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phb->lsi_table[i].qirq = qirq;
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}
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return 0;
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}
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static int spapr_main_pci_host_init(PCIDevice *d)
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{
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return 0;
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}
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static void spapr_main_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->init = spapr_main_pci_host_init;
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}
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static DeviceInfo spapr_main_pci_host_info = {
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.name = "spapr-pci-host-bridge-pci",
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.size = sizeof(PCIDevice),
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.class_init = spapr_main_pci_host_class_init,
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};
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static void spapr_phb_class_init(ObjectClass *klass, void *data)
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{
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SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
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sdc->init = spapr_phb_init;
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}
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static DeviceInfo spapr_phb_info = {
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.name = "spapr-pci-host-bridge",
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.size = sizeof(sPAPRPHBState),
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.class_init = spapr_phb_class_init,
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};
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static void spapr_register_devices(void)
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{
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sysbus_qdev_register(&spapr_phb_info);
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pci_qdev_register(&spapr_main_pci_host_info);
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}
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device_init(spapr_register_devices)
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static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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switch (size) {
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case 1:
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return cpu_inb(addr);
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case 2:
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return cpu_inw(addr);
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case 4:
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return cpu_inl(addr);
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}
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assert(0);
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}
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static void spapr_io_write(void *opaque, target_phys_addr_t addr,
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uint64_t data, unsigned size)
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{
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switch (size) {
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case 1:
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cpu_outb(addr, data);
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return;
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case 2:
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cpu_outw(addr, data);
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return;
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case 4:
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cpu_outl(addr, data);
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return;
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}
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assert(0);
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}
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static MemoryRegionOps spapr_io_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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.read = spapr_io_read,
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.write = spapr_io_write
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};
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void spapr_create_phb(sPAPREnvironment *spapr,
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const char *busname, uint64_t buid,
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uint64_t mem_win_addr, uint64_t mem_win_size,
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uint64_t io_win_addr)
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{
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DeviceState *dev;
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SysBusDevice *s;
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sPAPRPHBState *phb;
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PCIBus *bus;
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char namebuf[strlen(busname)+11];
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dev = qdev_create(NULL, "spapr-pci-host-bridge");
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qdev_init_nofail(dev);
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s = sysbus_from_qdev(dev);
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phb = FROM_SYSBUS(sPAPRPHBState, s);
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phb->mem_win_addr = mem_win_addr;
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sprintf(namebuf, "%s-mem", busname);
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memory_region_init(&phb->memspace, namebuf, INT64_MAX);
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sprintf(namebuf, "%s-memwindow", busname);
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memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
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SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size);
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memory_region_add_subregion(get_system_memory(), mem_win_addr,
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&phb->memwindow);
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phb->io_win_addr = io_win_addr;
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/* On ppc, we only have MMIO no specific IO space from the CPU
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* perspective. In theory we ought to be able to embed the PCI IO
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* memory region direction in the system memory space. However,
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* if any of the IO BAR subregions use the old_portio mechanism,
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* that won't be processed properly unless accessed from the
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* system io address space. This hack to bounce things via
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* system_io works around the problem until all the users of
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* old_portion are updated */
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sprintf(namebuf, "%s-io", busname);
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memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
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/* FIXME: fix to support multiple PHBs */
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memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
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sprintf(namebuf, "%s-iowindow", busname);
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memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
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namebuf, SPAPR_PCI_IO_WIN_SIZE);
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memory_region_add_subregion(get_system_memory(), io_win_addr,
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&phb->iowindow);
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phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname,
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pci_spapr_set_irq,
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pci_spapr_map_irq,
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phb,
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&phb->memspace, &phb->iospace,
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PCI_DEVFN(0, 0),
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SPAPR_PCI_NUM_LSI);
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spapr_rtas_register("read-pci-config", rtas_read_pci_config);
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spapr_rtas_register("write-pci-config", rtas_write_pci_config);
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spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
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spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
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QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
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/* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
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}
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/* Macros to operate with address in OF binding to PCI */
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#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
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#define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
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#define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
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#define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
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#define b_ss(x) b_x((x), 24, 2) /* the space code */
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#define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
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#define b_ddddd(x) b_x((x), 11, 5) /* device number */
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#define b_fff(x) b_x((x), 8, 3) /* function number */
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#define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
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int spapr_populate_pci_devices(sPAPRPHBState *phb,
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uint32_t xics_phandle,
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void *fdt)
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{
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PCIBus *bus = phb->host_state.bus;
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int bus_off, i;
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char nodename[256];
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uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
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struct {
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uint32_t hi;
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uint64_t child;
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uint64_t parent;
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uint64_t size;
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} __attribute__((packed)) ranges[] = {
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{
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cpu_to_be32(b_ss(1)), cpu_to_be64(0),
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cpu_to_be64(phb->io_win_addr),
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cpu_to_be64(memory_region_size(&phb->iospace)),
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},
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{
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cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
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cpu_to_be64(phb->mem_win_addr),
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cpu_to_be64(memory_region_size(&phb->memwindow)),
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},
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};
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uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
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uint32_t interrupt_map_mask[] = {
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cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, 0x0};
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uint32_t interrupt_map[bus->nirq][7];
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/* Start populating the FDT */
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sprintf(nodename, "pci@%" PRIx64, phb->buid);
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bus_off = fdt_add_subnode(fdt, 0, nodename);
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if (bus_off < 0) {
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return bus_off;
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}
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#define _FDT(exp) \
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do { \
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int ret = (exp); \
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if (ret < 0) { \
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return ret; \
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} \
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} while (0)
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/* Write PHB properties */
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_FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
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_FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
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_FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
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_FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
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_FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
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_FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
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_FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
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_FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
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_FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
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_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
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/* Build the interrupt-map, this must matches what is done
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* in pci_spapr_map_irq
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*/
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_FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
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&interrupt_map_mask, sizeof(interrupt_map_mask)));
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for (i = 0; i < 7; i++) {
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uint32_t *irqmap = interrupt_map[i];
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irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
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irqmap[1] = 0;
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irqmap[2] = 0;
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irqmap[3] = 0;
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irqmap[4] = cpu_to_be32(xics_phandle);
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irqmap[5] = cpu_to_be32(phb->lsi_table[i % SPAPR_PCI_NUM_LSI].dt_irq);
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irqmap[6] = cpu_to_be32(0x8);
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}
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/* Write interrupt map */
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_FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
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7 * sizeof(interrupt_map[0])));
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return 0;
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}
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