fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/*
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* OpenRISC interrupt.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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#include "qemu/host-utils.h"
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#ifndef CONFIG_USER_ONLY
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#include "hw/loader.h"
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#endif
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void openrisc_cpu_do_interrupt(CPUState *cs)
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{
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#ifndef CONFIG_USER_ONLY
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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CPUOpenRISCState *env = &cpu->env;
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env->epcr = env->pc;
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if (env->flags & D_FLAG) {
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env->flags &= ~D_FLAG;
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env->sr |= SR_DSX;
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env->epcr -= 4;
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}
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if (cs->exception_index == EXCP_SYSCALL) {
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env->epcr += 4;
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}
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/* For machine-state changed between user-mode and supervisor mode,
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we need flush TLB when we enter&exit EXCP. */
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tlb_flush(cs, 1);
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env->esr = env->sr;
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env->sr &= ~SR_DME;
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env->sr &= ~SR_IME;
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env->sr |= SR_SM;
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env->sr &= ~SR_IEE;
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env->sr &= ~SR_TEE;
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env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
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env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
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if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
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env->pc = (cs->exception_index << 8);
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} else {
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cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
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}
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#endif
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cs->exception_index = -1;
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}
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bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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CPUOpenRISCState *env = &cpu->env;
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int idx = -1;
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if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) {
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idx = EXCP_INT;
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}
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if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) {
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idx = EXCP_TICK;
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}
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if (idx >= 0) {
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cs->exception_index = idx;
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openrisc_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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