565 lines
24 KiB
Plaintext
565 lines
24 KiB
Plaintext
#
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# HPPA instruction decode definitions.
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#
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# Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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####
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# Field definitions
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####
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%assemble_sr3 13:1 14:2
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%assemble_sr3x 13:1 14:2 !function=expand_sr3x
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%assemble_11a 0:s1 4:10 !function=expand_shl3
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%assemble_12 0:s1 2:1 3:10 !function=expand_shl2
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%assemble_12a 0:s1 3:11 !function=expand_shl2
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%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
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%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2
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%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11
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%lowsign_11 0:s1 1:10
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%lowsign_14 0:s1 1:13
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%sm_imm 16:10 !function=expand_sm_imm
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%rm64 1:1 16:5
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%rt64 6:1 0:5
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%ra64 7:1 21:5
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%rb64 12:1 16:5
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%rc64 8:1 13:3 9:2
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%rc32 13:3 9:2
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%im5_0 0:s1 1:4
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%im5_16 16:s1 17:4
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%len5 0:5 !function=assemble_6
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%len6_8 8:1 0:5 !function=assemble_6
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%len6_12 12:1 0:5 !function=assemble_6
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%cpos6_11 11:1 5:5
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%ma_to_m 5:1 13:1 !function=ma_to_m
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%ma2_to_m 2:2 !function=ma_to_m
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%pos_to_m 0:1 !function=pos_to_m
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%neg_to_m 0:1 !function=neg_to_m
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%a_to_m 2:1 !function=neg_to_m
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%cmpbid_c 13:2 !function=cmpbid_c
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####
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# Argument set definitions
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####
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# All insns that need to form a virtual address should use this set.
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&ldst t b x disp sp m scale size
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&rr_cf_d t r cf d
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&rrr_cf t r1 r2 cf
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&rrr_cf_d t r1 r2 cf d
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&rrr_cf_d_sh t r1 r2 cf d sh
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&rri_cf t r i cf
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&rri_cf_d t r i cf d
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&rrb_c_f disp n c f r1 r2
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&rrb_c_d_f disp n c d f r1 r2
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&rib_c_f disp n c f r i
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&rib_c_d_f disp n c d f r i
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####
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# Format definitions
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####
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@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d
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@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
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@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
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@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh
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@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0
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@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
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@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11
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@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \
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&rrb_c_f disp=%assemble_12
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@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \
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&rrb_c_d_f disp=%assemble_12
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@rib_cf ...... r:5 ..... c:3 ........... n:1 . \
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&rib_c_f disp=%assemble_12 i=%im5_16
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@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \
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&rib_c_d_f disp=%assemble_12 i=%im5_16
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####
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# System
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####
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break 000000 ----- ----- --- 00000000 -----
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mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3
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mtctl 000000 t:5 r:5 --- 11000010 00000
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mtsarcm 000000 01011 r:5 --- 11000110 00000
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mtsm 000000 00000 r:5 000 11000011 00000
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mfia 000000 ----- 00000 --- 10100101 t:5
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mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3
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mfctl 000000 r:5 00000- e:1 -01000101 t:5
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sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma
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ldsid 000000 b:5 ----- sp:2 0 10000101 t:5
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rsm 000000 .......... 000 01110011 t:5 i=%sm_imm
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ssm 000000 .......... 000 01101011 t:5 i=%sm_imm
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rfi 000000 ----- ----- --- 01100000 00000
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rfi_r 000000 ----- ----- --- 01100101 00000
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# These are artificial instructions used by QEMU firmware.
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# They are allocated from the unassigned instruction space.
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halt 1111 1111 1111 1101 1110 1010 1101 0000
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reset 1111 1111 1111 1101 1110 1010 1101 0001
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getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010
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####
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# Memory Management
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####
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@addrx ...... b:5 x:5 .. ........ m:1 ..... \
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&ldst disp=0 scale=0 t=0 sp=0 size=0
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nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp
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nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index
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nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce
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nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a
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nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f
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nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice
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nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc
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probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5
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ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1
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ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
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sp=%assemble_sr3x data=0
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# pcxl and pcxl2 Fast TLB Insert instructions
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ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000
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pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
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pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
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sp=%assemble_sr3x data=0
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lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \
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&ldst disp=0 scale=0 size=0
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lci 000001 ----- ----- -- 01001100 0 t:5
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####
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# Arith/Log
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####
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andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d
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and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d
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or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d
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xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d
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uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d
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ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
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cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d
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uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d
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uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d
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dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d
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dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d
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add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh
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add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh
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add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh
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add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
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add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0
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sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d
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sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d
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sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d
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sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d
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sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d
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sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d
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ldil 001000 t:5 ..................... i=%assemble_21
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addil 001010 r:5 ..................... i=%assemble_21
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ldo 001101 b:5 t:5 -- .............. i=%lowsign_14
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addi 101101 ..... ..... .... 0 ........... @rri_cf
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addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf
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addi_tc 101100 ..... ..... .... 0 ........... @rri_cf
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addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf
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subi 100101 ..... ..... .... 0 ........... @rri_cf
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subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf
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cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d
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####
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# Index Mem
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####
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@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0
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@ldim5 ...... b:5 ..... sp:2 ......... t:5 \
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&ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m
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@stim5 ...... b:5 t:5 sp:2 ......... ..... \
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&ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m
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ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5
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ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx
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st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5
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ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2
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ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2
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ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3
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ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3
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lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2
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lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
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lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3
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lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3
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sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
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sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3
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stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
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@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \
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&ldst t=%rt64 disp=0 size=2
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@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \
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&ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2
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fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx
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fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi
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fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx
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fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi
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@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \
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&ldst disp=0 size=3
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@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \
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&ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3
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fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx
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fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi
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fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx
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fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
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####
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# Offset Mem
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####
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@ldstim11 ...... b:5 t:5 sp:2 .............. \
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&ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
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@ldstim14 ...... b:5 t:5 sp:2 .............. \
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&ldst disp=%lowsign_14 x=0 scale=0 m=0
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@ldstim14m ...... b:5 t:5 sp:2 .............. \
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&ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m
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@ldstim12m ...... b:5 t:5 sp:2 .............. \
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&ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
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# LDB, LDH, LDW, LDWM
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ld 010000 ..... ..... .. .............. @ldstim14 size=0
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ld 010001 ..... ..... .. .............. @ldstim14 size=1
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ld 010010 ..... ..... .. .............. @ldstim14 size=2
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ld 010011 ..... ..... .. .............. @ldstim14m size=2
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ld 010111 ..... ..... .. ...........10. @ldstim12m size=2
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# STB, STH, STW, STWM
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st 011000 ..... ..... .. .............. @ldstim14 size=0
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st 011001 ..... ..... .. .............. @ldstim14 size=1
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st 011010 ..... ..... .. .............. @ldstim14 size=2
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st 011011 ..... ..... .. .............. @ldstim14m size=2
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st 011111 ..... ..... .. ...........10. @ldstim12m size=2
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fldw 010110 b:5 ..... sp:2 .............. \
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&ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
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fldw 010111 b:5 ..... sp:2 ...........0.. \
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&ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
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fstw 011110 b:5 ..... sp:2 .............. \
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&ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
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fstw 011111 b:5 ..... sp:2 ...........0.. \
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&ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
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ld 010100 ..... ..... .. ............0. @ldstim11
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fldd 010100 ..... ..... .. ............1. @ldstim11
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st 011100 ..... ..... .. ............0. @ldstim11
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fstd 011100 ..... ..... .. ............1. @ldstim11
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####
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# Floating-point Multiply Add
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####
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&mpyadd rm1 rm2 ta ra tm
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@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd
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fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd
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fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd
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fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd
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fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
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####
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# Conditional Branches
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####
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bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
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bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
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movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
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movbi 110011 ..... ..... ... ........... . . @rib_cf f=0
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cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0
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cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1
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cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0
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cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1
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cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0
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cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1
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cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \
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&rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16
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addb 101000 ..... ..... ... ........... . . @rrb_cf f=0
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addb 101010 ..... ..... ... ........... . . @rrb_cf f=1
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addbi 101001 ..... ..... ... ........... . . @rib_cf f=0
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addbi 101011 ..... ..... ... ........... . . @rib_cf f=1
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####
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# Shift, Extract, Deposit
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####
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shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5
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shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5
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extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5
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extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5
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dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5
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dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8
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dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5
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dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \
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d=1 len=%len6_12 cpos=%cpos6_11
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depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \
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i=%im5_16 len=%len6_8
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depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \
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d=0 i=%im5_16 len=%len5
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depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \
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d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11
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####
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# Branch External
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####
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&BE b l n disp sp
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@be ...... b:5 ..... ... ........... n:1 . \
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&BE disp=%assemble_17 sp=%assemble_sr3
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be 111000 ..... ..... ... ........... . . @be l=0
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be 111001 ..... ..... ... ........... . . @be l=31
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####
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# Branch
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####
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&BL l n disp
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@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17
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# B,L and B,L,PUSH
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bl 111010 ..... ..... 000 ........... . . @bl
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bl 111010 ..... ..... 100 ........... . . @bl
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# B,L (long displacement)
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bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \
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disp=%assemble_22
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b_gate 111010 ..... ..... 001 ........... . . @bl
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blr 111010 l:5 x:5 010 00000000000 n:1 0
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bv 111010 b:5 x:5 110 00000000000 n:1 0
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bve 111010 b:5 00000 110 10000000000 n:1 - l=0
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bve 111010 b:5 00000 111 10000000000 n:1 - l=2
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####
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# FP Fused Multiple-Add
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####
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fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \
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rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64
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fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32
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####
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# FP operations
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####
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&fclass01 r t
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&fclass2 r1 r2 c y
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&fclass3 r1 r2 t
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@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01
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@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01
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@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2
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@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3
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@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \
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&fclass01 r=%ra64 t=%rt64
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@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01
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@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \
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&fclass01 r=%ra64 t=%rt64
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@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64
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@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64
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@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01
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@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \
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&fclass2 r1=%ra64 r2=%rb64
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@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2
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@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \
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&fclass3 r1=%ra64 r2=%rb64 t=%rt64
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@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5
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# Floating point class 0
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fid_f 001100 00000 00000 000 00 000000 00000
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fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0
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fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0
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fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0
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frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0
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fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0
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fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0
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fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0
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fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0
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fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0
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frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0
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fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0
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fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0
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fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0
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fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0
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fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0
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frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0
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fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0
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fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0
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fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0
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fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0
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fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0
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frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0
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fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0
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fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0
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# Floating point class 1
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# float/float
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fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1
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fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1
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fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1
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fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1
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# int/float
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fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1
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fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1
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fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1
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fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1
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fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1
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fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1
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fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1
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fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1
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# float/int
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|
fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1
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fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1
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fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1
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fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1
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|
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fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1
|
|
fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1
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|
fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1
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|
fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1
|
|
|
|
# float/int truncate
|
|
fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1
|
|
fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1
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|
fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1
|
|
fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1
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|
|
|
fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1
|
|
fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1
|
|
fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1
|
|
fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1
|
|
|
|
# uint/float
|
|
fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1
|
|
fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1
|
|
fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1
|
|
fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1
|
|
|
|
fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1
|
|
fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1
|
|
fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1
|
|
fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1
|
|
|
|
# float/int
|
|
fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1
|
|
fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1
|
|
fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1
|
|
fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1
|
|
|
|
fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1
|
|
fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1
|
|
fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1
|
|
fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1
|
|
|
|
# float/int truncate
|
|
fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1
|
|
fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1
|
|
fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1
|
|
fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1
|
|
|
|
fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1
|
|
fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1
|
|
fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1
|
|
fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1
|
|
|
|
# Floating point class 2
|
|
|
|
ftest 001100 00000 00000 y:3 00 10000 1 c:5
|
|
|
|
fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2
|
|
fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2
|
|
|
|
fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2
|
|
fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2
|
|
|
|
# Floating point class 3
|
|
|
|
fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3
|
|
fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3
|
|
fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3
|
|
fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3
|
|
|
|
fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3
|
|
fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3
|
|
fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3
|
|
fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3
|
|
|
|
fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3
|
|
fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3
|
|
fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3
|
|
fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3
|
|
|
|
fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3
|
|
fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3
|
|
fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3
|
|
fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3
|
|
|
|
xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64
|
|
|
|
# diag
|
|
diag 000101 i:26
|