Jiaxun Yang 6902759965 hw/intc/loongson_liointc: Fix per core ISR handling
Per core ISR is a set of 32-bit registers spaced by 8 bytes.
This patch fixed calculation of it's size and also added check
of alignment at reading & writing.

Fixes: Coverity CID 1438965 and CID 1438967
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Message-Id: <20210112012527.28927-1-jiaxun.yang@flygoat.com>
[PMD: Added Coverity CID]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21 18:41:46 +01:00
..
2020-12-10 12:15:08 -05:00
2021-01-08 15:13:38 +00:00
2020-09-09 09:27:09 -04:00
2020-09-09 09:27:09 -04:00
2021-01-08 15:13:38 +00:00
2020-12-14 15:54:12 +11:00
2020-09-09 09:27:09 -04:00