qemu/target
David Gibson 7222b94a83 target/ppc: Cleanup HPTE accessors for 64-bit hash MMU
Accesses to the hashed page table (HPT) are complicated by the fact that
the HPT could be in one of three places:
   1) Within guest memory - when we're emulating a full guest CPU at the
      hardware level (e.g. powernv, mac99, g3beige)
   2) Within qemu, but outside guest memory - when we're emulating user and
      supervisor instructions within TCG, but instead of emulating
      the CPU's hypervisor mode, we just emulate a hypervisor's behaviour
      (pseries in TCG or KVM-PR)
   3) Within the host kernel - a pseries machine using KVM-HV
      acceleration.  Mostly accesses to the HPT are handled by KVM,
      but there are a few cases where qemu needs to access it via a
      special fd for the purpose.

In order to batch accesses to the fd in case (3), we use a somewhat awkward
ppc_hash64_start_access() / ppc_hash64_stop_access() pair, which for case
(3) reads / releases several HPTEs from the kernel as a batch (usually a
whole PTEG).  For cases (1) & (2) it just returns an address value.  The
actual HPTE load helpers then need to interpret the returned token
differently in the 3 cases.

This patch keeps the same basic structure, but simplfiies the details.
First start_access() / stop_access() are renamed to map_hptes() and
unmap_hptes() to make their operation more obvious.  Second, map_hptes()
now always returns a qemu pointer, which can always be used in the same way
by the load_hpte() helpers.  In case (1) it comes from address_space_map()
in case (2) directly from qemu's HPT buffer and in case (3) from a
temporary buffer read from the KVM fd.

While we're at it, make things a bit more consistent in terms of types and
variable names: avoid variables named 'index' (it shadows index(3) which
can lead to confusing results), use 'hwaddr ptex' for HPTE indices and
uint64_t for each of the HPTE words, use ptex throughout the call stack
instead of pte_offset in some places (we still need that at the bottom
layer, but nowhere else).

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-01 11:23:39 +11:00
..
alpha target/alpha: Enable MTTCG by default 2017-02-28 11:41:46 +11:00
arm armv7m: Raise correct kind of UsageFault for attempts to execute ARM code 2017-02-28 12:08:19 +00:00
cris qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
hppa target/hppa: Fix gdb_write_register 2017-02-06 18:25:31 -08:00
i386 linux-user: Add signal handling support for x86_64 2017-02-27 23:10:02 +01:00
lm32 qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
m68k This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
microblaze cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
mips target-mips: Provide function to test if a CPU supports an ISA 2017-02-21 22:24:58 +00:00
moxie qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
nios2 nios2: Add architecture emulation support 2017-01-24 13:10:35 -08:00
openrisc target/openrisc: Optimize for r0 being zero 2017-02-14 08:15:00 +11:00
ppc target/ppc: Cleanup HPTE accessors for 64-bit hash MMU 2017-03-01 11:23:39 +11:00
s390x target/s390x: Fix typo 2017-02-28 09:03:38 +03:00
sh4 monitor: Fix crashes when using HMP commands without CPU 2017-02-21 18:29:01 +00:00
sparc cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap 2017-02-24 10:32:46 +00:00
tilegx qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
tricore qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
unicore32 cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
xtensa monitor: Fix crashes when using HMP commands without CPU 2017-02-21 18:29:01 +00:00