50c8d9bfc6
Map the I/O interruption code before calling into css. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
231 lines
6.6 KiB
C
231 lines
6.6 KiB
C
/*
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* S/390 channel I/O instructions
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*
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* Copyright 2012 IBM Corp.
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* Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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#ifndef IOINST_S390X_H
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#define IOINST_S390X_H
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/*
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* Channel I/O related definitions, as defined in the Principles
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* Of Operation (and taken from the Linux implementation).
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*/
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/* subchannel status word (command mode only) */
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typedef struct SCSW {
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uint16_t flags;
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uint16_t ctrl;
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uint32_t cpa;
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uint8_t dstat;
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uint8_t cstat;
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uint16_t count;
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} QEMU_PACKED SCSW;
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#define SCSW_FLAGS_MASK_KEY 0xf000
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#define SCSW_FLAGS_MASK_SCTL 0x0800
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#define SCSW_FLAGS_MASK_ESWF 0x0400
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#define SCSW_FLAGS_MASK_CC 0x0300
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#define SCSW_FLAGS_MASK_FMT 0x0080
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#define SCSW_FLAGS_MASK_PFCH 0x0040
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#define SCSW_FLAGS_MASK_ISIC 0x0020
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#define SCSW_FLAGS_MASK_ALCC 0x0010
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#define SCSW_FLAGS_MASK_SSI 0x0008
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#define SCSW_FLAGS_MASK_ZCC 0x0004
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#define SCSW_FLAGS_MASK_ECTL 0x0002
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#define SCSW_FLAGS_MASK_PNO 0x0001
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#define SCSW_CTRL_MASK_FCTL 0x7000
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#define SCSW_CTRL_MASK_ACTL 0x0fe0
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#define SCSW_CTRL_MASK_STCTL 0x001f
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#define SCSW_FCTL_CLEAR_FUNC 0x1000
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#define SCSW_FCTL_HALT_FUNC 0x2000
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#define SCSW_FCTL_START_FUNC 0x4000
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#define SCSW_ACTL_SUSP 0x0020
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#define SCSW_ACTL_DEVICE_ACTIVE 0x0040
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#define SCSW_ACTL_SUBCH_ACTIVE 0x0080
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#define SCSW_ACTL_CLEAR_PEND 0x0100
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#define SCSW_ACTL_HALT_PEND 0x0200
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#define SCSW_ACTL_START_PEND 0x0400
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#define SCSW_ACTL_RESUME_PEND 0x0800
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#define SCSW_STCTL_STATUS_PEND 0x0001
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#define SCSW_STCTL_SECONDARY 0x0002
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#define SCSW_STCTL_PRIMARY 0x0004
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#define SCSW_STCTL_INTERMEDIATE 0x0008
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#define SCSW_STCTL_ALERT 0x0010
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#define SCSW_DSTAT_ATTENTION 0x80
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#define SCSW_DSTAT_STAT_MOD 0x40
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#define SCSW_DSTAT_CU_END 0x20
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#define SCSW_DSTAT_BUSY 0x10
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#define SCSW_DSTAT_CHANNEL_END 0x08
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#define SCSW_DSTAT_DEVICE_END 0x04
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#define SCSW_DSTAT_UNIT_CHECK 0x02
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#define SCSW_DSTAT_UNIT_EXCEP 0x01
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#define SCSW_CSTAT_PCI 0x80
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#define SCSW_CSTAT_INCORR_LEN 0x40
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#define SCSW_CSTAT_PROG_CHECK 0x20
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#define SCSW_CSTAT_PROT_CHECK 0x10
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#define SCSW_CSTAT_DATA_CHECK 0x08
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#define SCSW_CSTAT_CHN_CTRL_CHK 0x04
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#define SCSW_CSTAT_INTF_CTRL_CHK 0x02
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#define SCSW_CSTAT_CHAIN_CHECK 0x01
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/* path management control word */
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typedef struct PMCW {
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uint32_t intparm;
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uint16_t flags;
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uint16_t devno;
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uint8_t lpm;
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uint8_t pnom;
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uint8_t lpum;
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uint8_t pim;
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uint16_t mbi;
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uint8_t pom;
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uint8_t pam;
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uint8_t chpid[8];
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uint32_t chars;
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} QEMU_PACKED PMCW;
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#define PMCW_FLAGS_MASK_QF 0x8000
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#define PMCW_FLAGS_MASK_W 0x4000
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#define PMCW_FLAGS_MASK_ISC 0x3800
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#define PMCW_FLAGS_MASK_ENA 0x0080
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#define PMCW_FLAGS_MASK_LM 0x0060
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#define PMCW_FLAGS_MASK_MME 0x0018
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#define PMCW_FLAGS_MASK_MP 0x0004
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#define PMCW_FLAGS_MASK_TF 0x0002
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#define PMCW_FLAGS_MASK_DNV 0x0001
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#define PMCW_FLAGS_MASK_INVALID 0x0700
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#define PMCW_CHARS_MASK_ST 0x00e00000
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#define PMCW_CHARS_MASK_MBFC 0x00000004
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#define PMCW_CHARS_MASK_XMWME 0x00000002
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#define PMCW_CHARS_MASK_CSENSE 0x00000001
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#define PMCW_CHARS_MASK_INVALID 0xff1ffff8
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/* subchannel information block */
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typedef struct SCHIB {
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PMCW pmcw;
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SCSW scsw;
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uint64_t mba;
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uint8_t mda[4];
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} QEMU_PACKED SCHIB;
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/* interruption response block */
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typedef struct IRB {
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SCSW scsw;
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uint32_t esw[5];
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uint32_t ecw[8];
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uint32_t emw[8];
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} QEMU_PACKED IRB;
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/* operation request block */
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typedef struct ORB {
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uint32_t intparm;
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uint16_t ctrl0;
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uint8_t lpm;
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uint8_t ctrl1;
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uint32_t cpa;
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} QEMU_PACKED ORB;
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#define ORB_CTRL0_MASK_KEY 0xf000
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#define ORB_CTRL0_MASK_SPND 0x0800
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#define ORB_CTRL0_MASK_STR 0x0400
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#define ORB_CTRL0_MASK_MOD 0x0200
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#define ORB_CTRL0_MASK_SYNC 0x0100
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#define ORB_CTRL0_MASK_FMT 0x0080
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#define ORB_CTRL0_MASK_PFCH 0x0040
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#define ORB_CTRL0_MASK_ISIC 0x0020
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#define ORB_CTRL0_MASK_ALCC 0x0010
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#define ORB_CTRL0_MASK_SSIC 0x0008
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#define ORB_CTRL0_MASK_C64 0x0002
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#define ORB_CTRL0_MASK_I2K 0x0001
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#define ORB_CTRL0_MASK_INVALID 0x0004
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#define ORB_CTRL1_MASK_ILS 0x80
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#define ORB_CTRL1_MASK_MIDAW 0x40
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#define ORB_CTRL1_MASK_ORBX 0x01
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#define ORB_CTRL1_MASK_INVALID 0x3e
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/* channel command word (type 1) */
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typedef struct CCW1 {
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uint8_t cmd_code;
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uint8_t flags;
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uint16_t count;
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uint32_t cda;
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} QEMU_PACKED CCW1;
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#define CCW_FLAG_DC 0x80
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#define CCW_FLAG_CC 0x40
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#define CCW_FLAG_SLI 0x20
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#define CCW_FLAG_SKIP 0x10
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#define CCW_FLAG_PCI 0x08
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#define CCW_FLAG_IDA 0x04
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#define CCW_FLAG_SUSPEND 0x02
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#define CCW_CMD_NOOP 0x03
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#define CCW_CMD_BASIC_SENSE 0x04
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#define CCW_CMD_TIC 0x08
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#define CCW_CMD_SENSE_ID 0xe4
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typedef struct CRW {
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uint16_t flags;
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uint16_t rsid;
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} QEMU_PACKED CRW;
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#define CRW_FLAGS_MASK_S 0x4000
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#define CRW_FLAGS_MASK_R 0x2000
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#define CRW_FLAGS_MASK_C 0x1000
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#define CRW_FLAGS_MASK_RSC 0x0f00
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#define CRW_FLAGS_MASK_A 0x0080
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#define CRW_FLAGS_MASK_ERC 0x003f
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#define CRW_ERC_INIT 0x02
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#define CRW_ERC_IPI 0x04
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#define CRW_RSC_SUBCH 0x3
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#define CRW_RSC_CHP 0x4
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/* I/O interruption code */
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typedef struct IOIntCode {
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uint32_t subsys_id;
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uint32_t intparm;
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uint32_t interrupt_id;
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} QEMU_PACKED IOIntCode;
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/* schid disintegration */
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#define IOINST_SCHID_ONE(_schid) ((_schid & 0x00010000) >> 16)
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#define IOINST_SCHID_M(_schid) ((_schid & 0x00080000) >> 19)
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#define IOINST_SCHID_CSSID(_schid) ((_schid & 0xff000000) >> 24)
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#define IOINST_SCHID_SSID(_schid) ((_schid & 0x00060000) >> 17)
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#define IOINST_SCHID_NR(_schid) (_schid & 0x0000ffff)
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int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
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int *schid);
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int ioinst_handle_xsch(CPUS390XState *env, uint64_t reg1);
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int ioinst_handle_csch(CPUS390XState *env, uint64_t reg1);
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int ioinst_handle_hsch(CPUS390XState *env, uint64_t reg1);
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int ioinst_handle_msch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
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int ioinst_handle_ssch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
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int ioinst_handle_stcrw(CPUS390XState *env, uint32_t ipb);
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int ioinst_handle_stsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
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int ioinst_handle_tsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
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int ioinst_handle_chsc(CPUS390XState *env, uint32_t ipb);
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int ioinst_handle_tpi(CPUS390XState *env, uint32_t ipb);
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int ioinst_handle_schm(CPUS390XState *env, uint64_t reg1, uint64_t reg2,
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uint32_t ipb);
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int ioinst_handle_rsch(CPUS390XState *env, uint64_t reg1);
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int ioinst_handle_rchp(CPUS390XState *env, uint64_t reg1);
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int ioinst_handle_sal(CPUS390XState *env, uint64_t reg1);
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#endif
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