Alistair Francis 70b78d4e71 hw/riscv: Allow 64 bit access to SiFive CLINT ...

Commit 5d971f9e672507210e77d020d89e0e89165c8fc9
"memory: Revert "memory: accept mismatching sizes in
memory_region_access_valid"" broke most RISC-V boards as they do 64 bit
accesses to the CLINT and QEMU would trigger a fault. Fix this failure
by allowing 8 byte accesses.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-Id: <122b78825b077e4dfd39b444d3a46fe894a7804c.1593547870.git.alistair.francis@wdc.com>

2020-07-02 09:19:32 -07:00

..

boot.c

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Kconfig

hw/char: Initial commit of Ibex UART

2020-06-19 08:24:07 -07:00

Makefile.objs

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opentitan.c

hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions

2020-06-19 08:24:07 -07:00

riscv_hart.c

riscv_hart: Fix riscv_harts_realize() error API violations

2020-07-02 06:25:29 +02:00

riscv_htif.c

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sifive_clint.c

hw/riscv: Allow 64 bit access to SiFive CLINT

2020-07-02 09:19:32 -07:00

sifive_e_prci.c

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sifive_e.c

hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004

2020-06-19 08:25:27 -07:00

sifive_gpio.c

hw/riscv: sifive_gpio: Do not blindly trigger output IRQs

2020-06-19 08:25:27 -07:00

sifive_plic.c

riscv: plic: Add a couple of mising sifive_plic_update calls

2020-07-02 09:19:32 -07:00

sifive_test.c

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sifive_u_otp.c

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sifive_u_prci.c

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sifive_u.c

riscv/sifive_u: Fix sifive_u_soc_realize() error API violations

2020-07-02 06:25:29 +02:00

sifive_uart.c

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spike.c

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trace-events

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virt.c

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