d5fee0bbe6
ISA V3.00 introduced a new radix mmu model. Implement the page fault handler for this so we can run a tcg guest in radix mode and perform address translation correctly. In real mode (mmu turned off) addresses are masked to remove the top 4 bits and then are subject to partition scoped translation, since we only support pseries at this stage it is only necessary to perform the masking and then we're done. In virtual mode (mmu turned on) address translation if performed as follows: 1. Use the quadrant to determine the fully qualified address. The fully qualified address is defined as the combination of the effective address, the effective logical partition id (LPID) and the effective process id (PID). Based on the quadrant (EA63:62) we set the pid and lpid like so: quadrant 0: lpid = LPIDR, pid = PIDR quadrant 1: HV only (not allowed in pseries) quadrant 2: HV only (not allowed in pseries) quadrant 3: lpid = LPIDR, pid = 0 If we can't get the fully qualified address we raise a segment interrupt. 2. Find the guest radix tree We ask the virtual hypervisor for the partition table which was registered with H_REGISTER_PROC_TBL which points us to the process table in guest memory. We then index this table by pid to get the process table entry which points us to the appropriate radix tree to translate the address. If the process table isn't big enough to contain an entry for the current pid then we raise a storage interrupt. 3. Walk the radix tree Next we walk the radix tree where each level is a table of page directory entries indexed by some number of bits from the effective address, where the number of bits is determined by the table size. We continue to walk the tree (while entries are valid and the table is of minimum size) until we reach a table of page table entries, indicated by having the leaf bit set. The appropriate pte is then checked for sufficient access permissions, the reference and change bits are updated and the real address is calculated from the real page number bits of the pte and the low bits of the effective address. If we can't find an entry or can't access the entry bacause of permissions then we raise a storage interrupt. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> [dwg: Add missing parentheses to macro] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
/*
|
|
* PowerPC ISAV3 BookS emulation generic mmu definitions for qemu.
|
|
*
|
|
* Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation
|
|
*
|
|
* This library is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
* License as published by the Free Software Foundation; either
|
|
* version 2 of the License, or (at your option) any later version.
|
|
*
|
|
* This library is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* Lesser General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#ifndef MMU_H
|
|
#define MMU_H
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
/* Partition Table Entry Fields */
|
|
#define PATBE1_GR 0x8000000000000000
|
|
|
|
/* Process Table Entry */
|
|
struct prtb_entry {
|
|
uint64_t prtbe0, prtbe1;
|
|
};
|
|
|
|
#ifdef TARGET_PPC64
|
|
|
|
static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
|
|
{
|
|
return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
|
|
}
|
|
|
|
static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
|
|
{
|
|
PPCVirtualHypervisorClass *vhc =
|
|
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
|
|
|
return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
|
|
}
|
|
|
|
int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
|
|
int mmu_idx);
|
|
|
|
#endif /* TARGET_PPC64 */
|
|
|
|
#endif /* CONFIG_USER_ONLY */
|
|
|
|
#endif /* MMU_H */
|