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70560da79d
qemu/target-ppc
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Fabien Chouteau 70560da79d Set an invalid-bits mask for each SPE instructions 
SPE instructions are defined by pairs. Currently, the invalid-bits mask is set
for the first instruction, but the second one can have a different mask.

example:
GEN_SPE(efdcmpeq,    efdcfs,      0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30 17:11:53 +01:00
..
cpu.h PPC: booke timers 2011-10-06 09:48:09 +02:00
helper_regs.h
helper.c pseries: Support SMT systems for KVM Book3S-HV 2011-10-30 17:11:53 +01:00
helper.h target-ppc: remove old CONFIG_SOFTFLOAT #ifdef 2011-06-03 16:07:48 +02:00
kvm_ppc.c PPC: KVM: Remove kvmppc_read_host_property 2011-10-06 09:43:35 +02:00
kvm_ppc.h pseries: Use Book3S-HV TCE acceleration capabilities 2011-10-30 17:11:53 +01:00
kvm.c pseries: Use Book3S-HV TCE acceleration capabilities 2011-10-30 17:11:53 +01:00
machine.c PPC: move TLBs to their own arrays 2011-06-17 02:58:37 +02:00
mfrom_table_gen.c
mfrom_table.c
op_helper.c softmmu_header: pass CPUState to tlb_fill 2011-10-01 09:31:26 +00:00
STATUS Fix typos in comments (chek -> check) 2011-05-22 22:31:45 +01:00
translate_init.c PPC: booke timers 2011-10-06 09:48:09 +02:00
translate.c Set an invalid-bits mask for each SPE instructions 2011-10-30 17:11:53 +01:00