qemu/target
Alexandre Ghiti 6f23aaeb9b
riscv: Allow user to set the satp mode
RISC-V specifies multiple sizes for addressable memory and Linux probes for
the machine's support at startup via the satp CSR register (done in
csr.c:validate_vm).

As per the specification, sv64 must support sv57, which in turn must
support sv48...etc. So we can restrict machine support by simply setting the
"highest" supported mode and the bare mode is always supported.

You can set the satp mode using the new properties "sv32", "sv39", "sv48",
"sv57" and "sv64" as follows:
-cpu rv64,sv57=on  # Linux will boot using sv57 scheme
-cpu rv64,sv39=on  # Linux will boot using sv39 scheme
-cpu rv64,sv57=off # Linux will boot using sv48 scheme
-cpu rv64          # Linux will boot using sv57 scheme by default

We take the highest level set by the user:
-cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme

We make sure that invalid configurations are rejected:
-cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are
                           # enabled

We accept "redundant" configurations:
-cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme

And contradictory configurations:
-cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme

Co-Developed-by: Ludovic Henry <ludovic@rivosinc.com>
Signed-off-by: Ludovic Henry <ludovic@rivosinc.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230303131252.892893-4-alexghiti@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06 08:09:42 -08:00
..
alpha accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
arm Monitor patches for 2023-03-02 2023-03-02 10:54:17 +00:00
avr accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
cris target/cris: Don't use tcg_temp_local_new 2023-03-01 07:33:28 -10:00
hexagon target/hexagon/idef-parser: Drop gen_tmp_local 2023-03-01 07:33:28 -10:00
hppa target/hppa: Don't use tcg_temp_local_new 2023-03-01 07:33:28 -10:00
i386 * bugfixes 2023-03-02 16:13:45 +00:00
loongarch target/loongarch: Implement Chip Configuraiton Version Register(0x0000) 2023-03-03 09:37:30 +08:00
m68k accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
microblaze accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
mips target/mips: Don't use tcg_temp_local_new 2023-03-01 07:33:28 -10:00
nios2 accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
openrisc accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
ppc target/ppc/translate: Add dummy implementation for dcblc instruction 2023-03-03 16:50:17 -03:00
riscv riscv: Allow user to set the satp mode 2023-03-06 08:09:42 -08:00
rx accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
s390x accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
sh4 accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
sparc accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
tricore accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
xtensa target/xtensa: Don't use tcg_temp_local_new_* 2023-03-01 07:33:28 -10:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00