6ee45fac56
Enforce the style described by commit 067109a11c ("docs/devel:
mention the spacing requirement for QOM"):
The first declaration of a storage or class structure should
always be the parent and leave a visual space between that
declaration and the new code. It is also useful to separate
backing for properties (options driven by the user) and internal
state to make navigation easier.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231013140116.255-2-philmd@linaro.org>
172 lines
4.7 KiB
C
172 lines
4.7 KiB
C
/*
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* RX emulation definition
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*
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* Copyright (c) 2019 Yoshinori Sato
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RX_CPU_H
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#define RX_CPU_H
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#include "qemu/bitops.h"
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#include "hw/registerfields.h"
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#include "qemu/cpu-float.h"
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/* PSW define */
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REG32(PSW, 0)
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FIELD(PSW, C, 0, 1)
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FIELD(PSW, Z, 1, 1)
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FIELD(PSW, S, 2, 1)
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FIELD(PSW, O, 3, 1)
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FIELD(PSW, I, 16, 1)
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FIELD(PSW, U, 17, 1)
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FIELD(PSW, PM, 20, 1)
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FIELD(PSW, IPL, 24, 4)
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/* FPSW define */
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REG32(FPSW, 0)
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FIELD(FPSW, RM, 0, 2)
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FIELD(FPSW, CV, 2, 1)
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FIELD(FPSW, CO, 3, 1)
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FIELD(FPSW, CZ, 4, 1)
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FIELD(FPSW, CU, 5, 1)
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FIELD(FPSW, CX, 6, 1)
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FIELD(FPSW, CE, 7, 1)
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FIELD(FPSW, CAUSE, 2, 6)
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FIELD(FPSW, DN, 8, 1)
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FIELD(FPSW, EV, 10, 1)
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FIELD(FPSW, EO, 11, 1)
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FIELD(FPSW, EZ, 12, 1)
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FIELD(FPSW, EU, 13, 1)
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FIELD(FPSW, EX, 14, 1)
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FIELD(FPSW, ENABLE, 10, 5)
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FIELD(FPSW, FV, 26, 1)
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FIELD(FPSW, FO, 27, 1)
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FIELD(FPSW, FZ, 28, 1)
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FIELD(FPSW, FU, 29, 1)
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FIELD(FPSW, FX, 30, 1)
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FIELD(FPSW, FLAGS, 26, 4)
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FIELD(FPSW, FS, 31, 1)
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enum {
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NUM_REGS = 16,
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};
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typedef struct CPUArchState {
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/* CPU registers */
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uint32_t regs[NUM_REGS]; /* general registers */
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uint32_t psw_o; /* O bit of status register */
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uint32_t psw_s; /* S bit of status register */
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uint32_t psw_z; /* Z bit of status register */
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uint32_t psw_c; /* C bit of status register */
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uint32_t psw_u;
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uint32_t psw_i;
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uint32_t psw_pm;
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uint32_t psw_ipl;
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uint32_t bpsw; /* backup status */
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uint32_t bpc; /* backup pc */
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uint32_t isp; /* global base register */
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uint32_t usp; /* vector base register */
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uint32_t pc; /* program counter */
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uint32_t intb; /* interrupt vector */
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uint32_t fintv;
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uint32_t fpsw;
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uint64_t acc;
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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/* Internal use */
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uint32_t in_sleep;
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uint32_t req_irq; /* Requested interrupt no (hard) */
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uint32_t req_ipl; /* Requested interrupt level */
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uint32_t ack_irq; /* execute irq */
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uint32_t ack_ipl; /* execute ipl */
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float_status fp_status;
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qemu_irq ack; /* Interrupt acknowledge */
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} CPURXState;
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/*
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* RXCPU:
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* @env: #CPURXState
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*
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* A RX CPU
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*/
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struct ArchCPU {
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CPUState parent_obj;
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CPURXState env;
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};
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#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
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#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
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#define CPU_RESOLVING_TYPE TYPE_RX_CPU
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const char *rx_crname(uint8_t cr);
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#ifndef CONFIG_USER_ONLY
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void rx_cpu_do_interrupt(CPUState *cpu);
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bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
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hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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#endif /* !CONFIG_USER_ONLY */
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void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void rx_translate_init(void);
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void rx_cpu_list(void);
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void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
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#define cpu_list rx_cpu_list
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#include "exec/cpu-all.h"
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#define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0
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#define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1
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#define RX_CPU_IRQ 0
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#define RX_CPU_FIR 1
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static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
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uint64_t *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
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*flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
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}
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static inline int cpu_mmu_index(CPURXState *env, bool ifetch)
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{
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return 0;
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}
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static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
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{
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uint32_t psw = 0;
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psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl);
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psw = FIELD_DP32(psw, PSW, PM, env->psw_pm);
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psw = FIELD_DP32(psw, PSW, U, env->psw_u);
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psw = FIELD_DP32(psw, PSW, I, env->psw_i);
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psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31);
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psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31);
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psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0);
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psw = FIELD_DP32(psw, PSW, C, env->psw_c);
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return psw;
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}
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#endif /* RX_CPU_H */
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