6ee45fac56
Enforce the style described by commit 067109a11c ("docs/devel:
mention the spacing requirement for QOM"):
The first declaration of a storage or class structure should
always be the parent and leave a visual space between that
declaration and the new code. It is also useful to separate
backing for properties (options driven by the user) and internal
state to make navigation easier.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231013140116.255-2-philmd@linaro.org>
181 lines
4.9 KiB
C
181 lines
4.9 KiB
C
/*
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* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_CPU_H
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#define HEXAGON_CPU_H
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#include "fpu/softfloat-types.h"
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#include "exec/cpu-defs.h"
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#include "hex_regs.h"
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#include "mmvec/mmvec.h"
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#include "qom/object.h"
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#include "hw/core/cpu.h"
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#include "hw/registerfields.h"
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#define NUM_PREGS 4
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#define TOTAL_PER_THREAD_REGS 64
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#define SLOTS_MAX 4
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#define STORES_MAX 2
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#define REG_WRITES_MAX 32
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#define PRED_WRITES_MAX 5 /* 4 insns + endloop */
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#define VSTORES_MAX 2
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#define TYPE_HEXAGON_CPU "hexagon-cpu"
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#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
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#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
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#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
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#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
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#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
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#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
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#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
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void hexagon_cpu_list(void);
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#define cpu_list hexagon_cpu_list
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#define MMU_USER_IDX 0
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typedef struct {
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target_ulong va;
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uint8_t width;
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uint32_t data32;
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uint64_t data64;
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} MemLog;
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typedef struct {
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target_ulong va;
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int size;
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DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16);
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MMVector data QEMU_ALIGNED(16);
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} VStoreLog;
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#define EXEC_STATUS_OK 0x0000
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#define EXEC_STATUS_STOP 0x0002
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#define EXEC_STATUS_REPLAY 0x0010
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#define EXEC_STATUS_LOCKED 0x0020
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#define EXEC_STATUS_EXCEPTION 0x0100
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#define EXCEPTION_DETECTED (env->status & EXEC_STATUS_EXCEPTION)
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#define REPLAY_DETECTED (env->status & EXEC_STATUS_REPLAY)
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#define CLEAR_EXCEPTION (env->status &= (~EXEC_STATUS_EXCEPTION))
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#define SET_EXCEPTION (env->status |= EXEC_STATUS_EXCEPTION)
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/* Maximum number of vector temps in a packet */
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#define VECTOR_TEMPS_MAX 4
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typedef struct CPUArchState {
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target_ulong gpr[TOTAL_PER_THREAD_REGS];
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target_ulong pred[NUM_PREGS];
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/* For comparing with LLDB on target - see adjust_stack_ptrs function */
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target_ulong last_pc_dumped;
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target_ulong stack_start;
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uint8_t slot_cancelled;
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target_ulong new_value_usr;
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/*
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* Only used when HEX_DEBUG is on, but unconditionally included
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* to reduce recompile time when turning HEX_DEBUG on/off.
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*/
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target_ulong reg_written[TOTAL_PER_THREAD_REGS];
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MemLog mem_log_stores[STORES_MAX];
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float_status fp_status;
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target_ulong llsc_addr;
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target_ulong llsc_val;
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uint64_t llsc_val_i64;
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MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16);
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MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
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MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
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MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16);
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MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16);
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/* Temporaries used within instructions */
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MMVectorPair VuuV QEMU_ALIGNED(16);
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MMVectorPair VvvV QEMU_ALIGNED(16);
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MMVectorPair VxxV QEMU_ALIGNED(16);
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MMVector vtmp QEMU_ALIGNED(16);
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MMQReg qtmp QEMU_ALIGNED(16);
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VStoreLog vstore[VSTORES_MAX];
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target_ulong vstore_pending[VSTORES_MAX];
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bool vtcm_pending;
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VTCMStoreLog vtcm_log;
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} CPUHexagonState;
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OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
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typedef struct HexagonCPUClass {
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CPUClass parent_class;
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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} HexagonCPUClass;
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struct ArchCPU {
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CPUState parent_obj;
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CPUHexagonState env;
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bool lldb_compat;
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target_ulong lldb_stack_adjust;
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bool short_circuit;
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};
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#include "cpu_bits.h"
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FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
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static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
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uint64_t *cs_base, uint32_t *flags)
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{
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uint32_t hex_flags = 0;
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*pc = env->gpr[HEX_REG_PC];
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*cs_base = 0;
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if (*pc == env->gpr[HEX_REG_SA0]) {
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hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
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}
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*flags = hex_flags;
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}
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static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
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{
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#ifdef CONFIG_USER_ONLY
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return MMU_USER_IDX;
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#else
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#error System mode not supported on Hexagon yet
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#endif
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}
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typedef HexagonCPU ArchCPU;
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void hexagon_translate_init(void);
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#include "exec/cpu-all.h"
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#endif /* HEXAGON_CPU_H */
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