6ebbf39000
allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
314 lines
11 KiB
C
314 lines
11 KiB
C
/*
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* Software MMU support
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define DATA_SIZE (1 << SHIFT)
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#if DATA_SIZE == 8
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#define SUFFIX q
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#define USUFFIX q
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#define DATA_TYPE uint64_t
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#elif DATA_SIZE == 4
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#define SUFFIX l
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#define USUFFIX l
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#define DATA_TYPE uint32_t
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#elif DATA_SIZE == 2
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#define SUFFIX w
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#define USUFFIX uw
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#define DATA_TYPE uint16_t
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#elif DATA_SIZE == 1
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#define SUFFIX b
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#define USUFFIX ub
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#define DATA_TYPE uint8_t
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#else
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#error unsupported data size
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#endif
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#ifdef SOFTMMU_CODE_ACCESS
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#define READ_ACCESS_TYPE 2
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#define ADDR_READ addr_code
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#else
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#define READ_ACCESS_TYPE 0
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#define ADDR_READ addr_read
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#endif
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static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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int mmu_idx,
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void *retaddr);
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static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
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target_ulong tlb_addr)
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{
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DATA_TYPE res;
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int index;
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index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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#if SHIFT <= 2
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res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
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#else
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#ifdef TARGET_WORDS_BIGENDIAN
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res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
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res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
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#else
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res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
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res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
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#endif
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#endif /* SHIFT > 2 */
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#ifdef USE_KQEMU
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env->last_io_time = cpu_get_time_fast();
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#endif
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return res;
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}
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/* handle all cases except unaligned access which span two pages */
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DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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int mmu_idx)
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{
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DATA_TYPE res;
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int index;
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target_ulong tlb_addr;
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target_phys_addr_t physaddr;
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void *retaddr;
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/* test if there is match for unaligned or IO access */
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/* XXX: could done more in memory macro in a non portable way */
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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physaddr = addr + env->tlb_table[mmu_idx][index].addend;
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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/* slow unaligned access (it spans two pages or IO) */
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do_unaligned_access:
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retaddr = GETPC();
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#ifdef ALIGNED_ONLY
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do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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#endif
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res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
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mmu_idx, retaddr);
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} else {
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/* unaligned/aligned access in the same page */
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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retaddr = GETPC();
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do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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}
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#endif
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res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
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}
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} else {
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/* the page is not in the TLB : fill it */
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retaddr = GETPC();
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0)
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do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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#endif
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tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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goto redo;
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}
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return res;
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}
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/* handle all unaligned cases */
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static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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int mmu_idx,
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void *retaddr)
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{
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DATA_TYPE res, res1, res2;
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int index, shift;
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target_phys_addr_t physaddr;
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target_ulong tlb_addr, addr1, addr2;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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physaddr = addr + env->tlb_table[mmu_idx][index].addend;
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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do_unaligned_access:
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/* slow unaligned access (it spans two pages) */
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addr1 = addr & ~(DATA_SIZE - 1);
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addr2 = addr1 + DATA_SIZE;
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res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
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mmu_idx, retaddr);
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res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
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mmu_idx, retaddr);
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shift = (addr & (DATA_SIZE - 1)) * 8;
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#ifdef TARGET_WORDS_BIGENDIAN
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res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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#else
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res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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#endif
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res = (DATA_TYPE)res;
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} else {
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/* unaligned/aligned access in the same page */
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res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
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}
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} else {
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/* the page is not in the TLB : fill it */
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tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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goto redo;
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}
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return res;
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}
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#ifndef SOFTMMU_CODE_ACCESS
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static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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DATA_TYPE val,
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int mmu_idx,
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void *retaddr);
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static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
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DATA_TYPE val,
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target_ulong tlb_addr,
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void *retaddr)
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{
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int index;
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index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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env->mem_write_vaddr = tlb_addr;
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env->mem_write_pc = (unsigned long)retaddr;
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#if SHIFT <= 2
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io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
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#else
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#ifdef TARGET_WORDS_BIGENDIAN
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io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
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io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
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#else
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io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
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io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
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#endif
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#endif /* SHIFT > 2 */
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#ifdef USE_KQEMU
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env->last_io_time = cpu_get_time_fast();
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#endif
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}
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void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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DATA_TYPE val,
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int mmu_idx)
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{
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target_phys_addr_t physaddr;
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target_ulong tlb_addr;
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void *retaddr;
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int index;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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physaddr = addr + env->tlb_table[mmu_idx][index].addend;
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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retaddr = GETPC();
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glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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do_unaligned_access:
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retaddr = GETPC();
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#ifdef ALIGNED_ONLY
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do_unaligned_access(addr, 1, mmu_idx, retaddr);
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#endif
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glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
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mmu_idx, retaddr);
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} else {
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/* aligned/unaligned access in the same page */
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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retaddr = GETPC();
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do_unaligned_access(addr, 1, mmu_idx, retaddr);
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}
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#endif
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glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
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}
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} else {
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/* the page is not in the TLB : fill it */
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retaddr = GETPC();
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0)
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do_unaligned_access(addr, 1, mmu_idx, retaddr);
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#endif
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tlb_fill(addr, 1, mmu_idx, retaddr);
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goto redo;
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}
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}
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/* handles all unaligned cases */
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static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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DATA_TYPE val,
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int mmu_idx,
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void *retaddr)
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{
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target_phys_addr_t physaddr;
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target_ulong tlb_addr;
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int index, i;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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physaddr = addr + env->tlb_table[mmu_idx][index].addend;
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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do_unaligned_access:
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/* XXX: not efficient, but simple */
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for(i = 0;i < DATA_SIZE; i++) {
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#ifdef TARGET_WORDS_BIGENDIAN
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glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
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mmu_idx, retaddr);
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#else
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glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
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mmu_idx, retaddr);
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#endif
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}
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} else {
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/* aligned/unaligned access in the same page */
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glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
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}
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} else {
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/* the page is not in the TLB : fill it */
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tlb_fill(addr, 1, mmu_idx, retaddr);
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goto redo;
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}
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}
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#endif /* !defined(SOFTMMU_CODE_ACCESS) */
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#undef READ_ACCESS_TYPE
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#undef SHIFT
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#undef DATA_TYPE
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#undef SUFFIX
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#undef USUFFIX
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#undef DATA_SIZE
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#undef ADDR_READ
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