55e5c28502
Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
91 lines
2.6 KiB
C
91 lines
2.6 KiB
C
/*
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* QEMU SuperH CPU
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*
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* Copyright (c) 2005 Samuel Tardieu
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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/* CPUClass::reset() */
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static void superh_cpu_reset(CPUState *s)
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{
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SuperHCPU *cpu = SUPERH_CPU(s);
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SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
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CPUSH4State *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(env, 0);
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}
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scc->parent_reset(s);
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memset(env, 0, offsetof(CPUSH4State, breakpoints));
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tlb_flush(env, 1);
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env->pc = 0xA0000000;
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#if defined(CONFIG_USER_ONLY)
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env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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#else
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env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
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env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
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set_float_rounding_mode(float_round_to_zero, &env->fp_status);
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set_flush_to_zero(1, &env->fp_status);
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#endif
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set_default_nan_mode(1, &env->fp_status);
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}
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static void superh_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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cpu_exec_init(env);
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env->movcal_backup_tail = &(env->movcal_backup);
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}
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static void superh_cpu_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->parent_reset = cc->reset;
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cc->reset = superh_cpu_reset;
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}
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static const TypeInfo superh_cpu_type_info = {
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.name = TYPE_SUPERH_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(SuperHCPU),
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.instance_init = superh_cpu_initfn,
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.abstract = false,
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.class_size = sizeof(SuperHCPUClass),
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.class_init = superh_cpu_class_init,
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};
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static void superh_cpu_register_types(void)
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{
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type_register_static(&superh_cpu_type_info);
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}
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type_init(superh_cpu_register_types)
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