Fabian Aggeler 6e8801f9de target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI ...

Add checks of SCR AW/FW bits when performing writes of CPSR.  These SCR bits
are used to control whether the CPSR masking bits can be adjusted from
non-secure state.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-15-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2014-12-11 12:07:50 +00:00

..

arm_ldst.h

…

arm-semi.c

Pass semihosting exit code back to system.

2014-12-11 12:07:48 +00:00

cpu64.c

target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"

2014-10-24 12:19:13 +01:00

cpu-qom.h

…

cpu.c

target-arm: add SCTLR_EL3 and make SCTLR banked

2014-12-11 12:07:50 +00:00

cpu.h

target-arm: add SCTLR_EL3 and make SCTLR banked

2014-12-11 12:07:50 +00:00

crypto_helper.c

…

gdbstub64.c

…

gdbstub.c

…

helper-a64.c

target-arm: rename arm_current_pl to arm_current_el

2014-10-24 12:19:14 +01:00

helper-a64.h

…

helper.c

target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI

2014-12-11 12:07:50 +00:00

helper.h

…

internals.h

target-arm: rename arm_current_pl to arm_current_el

2014-10-24 12:19:14 +01:00

iwmmxt_helper.c

…

kvm32.c

target-arm: add secure state bit to CPREG hash

2014-12-11 12:07:49 +00:00

kvm64.c

…

kvm_arm.h

…

kvm-consts.h

…

kvm-stub.c

…

kvm.c

…

machine.c

target-arm: increase arrays of registers R13 & R14

2014-10-24 12:19:14 +01:00

Makefile.objs

…

neon_helper.c

…

op_addsub.h

…

op_helper.c

target-arm: add SCTLR_EL3 and make SCTLR banked

2014-12-11 12:07:50 +00:00

psci.c

…

translate-a64.c

target-arm: A64: remove redundant store

2014-11-02 10:04:34 +03:00

translate.c

target-arm: add secure state bit to CPREG hash

2014-12-11 12:07:49 +00:00

translate.h

target-arm: add non-secure Translation Block flag

2014-12-11 12:07:48 +00:00