28e0204254
The code for -machine pseries maintains a global sPAPREnvironment structure which keeps track of general state information about the guest platform. This predates the existence of the MachineState structure, but performs basically the same function. Now that we have the generic MachineState, fold sPAPREnvironment into sPAPRMachineState, the pseries specific subclass of MachineState. This is mostly a matter of search and replace, although a few places which relied on the global spapr variable are changed to find the structure via qdev_get_machine(). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
142 lines
4.3 KiB
C
142 lines
4.3 KiB
C
/*
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* QEMU SPAPR PCI BUS definitions
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*
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* Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if !defined(__HW_SPAPR_H__)
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#error Please include spapr.h before this file!
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#endif
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#if !defined(__HW_SPAPR_PCI_H__)
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#define __HW_SPAPR_PCI_H__
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/xics.h"
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#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
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#define TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE "spapr-pci-vfio-host-bridge"
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#define SPAPR_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
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#define SPAPR_PCI_VFIO_HOST_BRIDGE(obj) \
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OBJECT_CHECK(sPAPRPHBVFIOState, (obj), TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE)
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#define SPAPR_PCI_HOST_BRIDGE_CLASS(klass) \
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OBJECT_CLASS_CHECK(sPAPRPHBClass, (klass), TYPE_SPAPR_PCI_HOST_BRIDGE)
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#define SPAPR_PCI_HOST_BRIDGE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(sPAPRPHBClass, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
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typedef struct sPAPRPHBClass sPAPRPHBClass;
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typedef struct sPAPRPHBState sPAPRPHBState;
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typedef struct sPAPRPHBVFIOState sPAPRPHBVFIOState;
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struct sPAPRPHBClass {
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PCIHostBridgeClass parent_class;
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void (*finish_realize)(sPAPRPHBState *sphb, Error **errp);
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int (*eeh_set_option)(sPAPRPHBState *sphb, unsigned int addr, int option);
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int (*eeh_get_state)(sPAPRPHBState *sphb, int *state);
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int (*eeh_reset)(sPAPRPHBState *sphb, int option);
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int (*eeh_configure)(sPAPRPHBState *sphb);
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};
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typedef struct spapr_pci_msi {
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uint32_t first_irq;
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uint32_t num;
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} spapr_pci_msi;
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typedef struct spapr_pci_msi_mig {
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uint32_t key;
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spapr_pci_msi value;
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} spapr_pci_msi_mig;
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struct sPAPRPHBState {
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PCIHostState parent_obj;
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uint32_t index;
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uint64_t buid;
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char *dtbusname;
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bool dr_enabled;
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MemoryRegion memspace, iospace;
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hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
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MemoryRegion memwindow, iowindow, msiwindow;
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uint32_t dma_liobn;
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AddressSpace iommu_as;
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MemoryRegion iommu_root;
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struct spapr_pci_lsi {
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uint32_t irq;
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} lsi_table[PCI_NUM_PINS];
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GHashTable *msi;
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/* Temporary cache for migration purposes */
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int32_t msi_devs_num;
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spapr_pci_msi_mig *msi_devs;
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QLIST_ENTRY(sPAPRPHBState) list;
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};
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struct sPAPRPHBVFIOState {
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sPAPRPHBState phb;
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int32_t iommugroupid;
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};
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#define SPAPR_PCI_MAX_INDEX 255
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#define SPAPR_PCI_BASE_BUID 0x800000020000000ULL
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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#define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL
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#define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL
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#define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000
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#define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \
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SPAPR_PCI_MEM_WIN_BUS_OFFSET)
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#define SPAPR_PCI_IO_WIN_OFF 0x80000000
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#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
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#define SPAPR_PCI_DMA32_SIZE 0x40000000
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static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
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}
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PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
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int spapr_populate_pci_dt(sPAPRPHBState *phb,
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uint32_t xics_phandle,
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void *fdt);
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void spapr_pci_msi_init(sPAPRMachineState *spapr, hwaddr addr);
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void spapr_pci_rtas_init(void);
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sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
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PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
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uint32_t config_addr);
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#endif /* __HW_SPAPR_PCI_H__ */
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