Peter Maydell 6d9571f7d8 target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
Implement the SIMD 3-reg-same instructions SQADD, UQADD,
SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL,
SQRSHL, UQRSHL; these are all simple calls to existing
Neon helpers. We also enable SSHL, USHL, SRSHL and URSHL
for the 3-reg-same-scalar category (but not the others
because they can have non-size-64 operands and the
scalar_3reg_same function doesn't support that yet.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08 14:46:55 +00:00
2014-01-31 22:05:03 +01:00
2014-02-08 13:12:50 +00:00
2014-02-08 13:12:50 +00:00
2014-02-07 16:42:13 +00:00
2014-02-07 16:42:13 +00:00
2014-01-31 11:13:08 +00:00
2014-02-01 13:45:20 +04:00
2014-02-07 16:03:13 +00:00
2014-01-08 19:07:20 +00:00
2014-01-10 11:04:31 -08:00
2014-02-05 16:37:26 +00:00
2014-01-24 17:40:03 +01:00
2014-02-01 13:46:06 +04:00
2013-12-04 15:19:00 +01:00
2013-12-04 15:19:00 +01:00

Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org

- QEMU team
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