qemu/tests/tcg/hexagon
Taylor Simpson a5a8d98c85 Hexagon (target/hexagon) fix l2fetch instructions
Y4_l2fetch == l2fetch(Rs32, Rt32)
Y5_l2fetch == l2fetch(Rs32, Rtt32)

The semantics for these instructions are present, but the encodings
are missing.

Note that these are treated as nops in qemu, so we add overrides.

Test case added to tests/tcg/hexagon/misc.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1622589584-22571-3-git-send-email-tsimpson@quicinc.com>
2021-06-29 11:32:50 -05:00
..
atomics.c Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc 2021-02-18 07:48:22 -08:00
brev.c Hexagon (target/hexagon) bit reverse (brev) addressing 2021-05-01 16:03:10 -07:00
circ.c Hexagon (target/hexagon) circular addressing 2021-05-01 16:01:39 -07:00
dual_stores.c Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc 2021-02-18 07:48:22 -08:00
first.S Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc 2021-02-18 07:48:22 -08:00
float_convs.ref
float_madds.ref
fpstuff.c Hexagon (target/hexagon) add F2_sfinvsqrta 2021-05-01 08:31:43 -07:00
load_align.c Hexagon (target/hexagon) load into shifted register instructions 2021-05-01 16:06:11 -07:00
load_unpack.c Hexagon (target/hexagon) load and unpack bytes instructions 2021-05-01 16:06:09 -07:00
Makefile.target Hexagon (target/hexagon) load into shifted register instructions 2021-05-01 16:06:11 -07:00
mem_noshuf.c Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc 2021-02-18 07:48:22 -08:00
misc.c Hexagon (target/hexagon) fix l2fetch instructions 2021-06-29 11:32:50 -05:00
multi_result.c Hexagon (target/hexagon) add A4_addp_c/A4_subp_c 2021-05-01 08:31:43 -07:00
preg_alias.c Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc 2021-02-18 07:48:22 -08:00