2a5ee4e18d
The MPS2 SCC device is broadly the same for all FPGA images, but has
minor differences in the behaviour of the CFG registers depending on
the image. In many cases we don't really care about the functionality
controlled by these registers and a reads-as-written or similar
behaviour is sufficient for the moment.
For the AN536 the required behaviour is:
* A_CFG0 has CPU reset and halt bits
- implement as reads-as-written for the moment
* A_CFG1 has flash or ATCM address 0 remap handling
- QEMU doesn't model this; implement as reads-as-written
* A_CFG2 has QSPI select (like AN524)
- implemented (no behaviour, as with AN524)
* A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
- QEMU doesn't care about these, so use the existing
RAZ behaviour for convenience
* A_CFG4 is board rev (like all other images)
- no change needed
* A_CFG5 is ACLK frq in hz (like AN524)
- implemented as reads-as-written, as for other boards
* A_CFG6 is core 0 vector table base address
- implemented as reads-as-written for the moment
* A_CFG7 is core 1 vector table base address
- implemented as reads-as-written for the moment
Make the changes necessary for this; leave TODO comments where
appropriate to indicate where we might want to come back and
implement things like CPU reset.
The other aspects of the device specific to this FPGA image (like the
values of the board ID and similar registers) will be set via the
device's qdev properties.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
/*
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* ARM MPS2 SCC emulation
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*
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* Copyright (c) 2017 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the Serial Communication Controller (SCC)
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* block found in most MPS FPGA images.
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*
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* QEMU interface:
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* + sysbus MMIO region 0: the register bank
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* + QOM property "scc-cfg4": value of the read-only CFG4 register
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* + QOM property "scc-aid": value of the read-only SCC_AID register
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* + QOM property "scc-id": value of the read-only SCC_ID register
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* + QOM property "scc-cfg0": reset value of the CFG0 register
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* + QOM property array "oscclk": reset values of the OSCCLK registers
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* (which are accessed via the SYS_CFG channel provided by this device)
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* + named GPIO output "remap": this tracks the value of CFG0 register
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* bit 0. Boards where this bit controls memory remapping should
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* connect this GPIO line to a function performing that mapping.
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* Boards where bit 0 has no special function should leave the GPIO
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* output disconnected.
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*/
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#ifndef MPS2_SCC_H
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#define MPS2_SCC_H
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#include "hw/sysbus.h"
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#include "hw/misc/led.h"
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#include "qom/object.h"
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#define TYPE_MPS2_SCC "mps2-scc"
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OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC)
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struct MPS2SCC {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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LEDState *led[8];
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uint32_t cfg0;
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uint32_t cfg1;
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uint32_t cfg2;
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uint32_t cfg4;
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uint32_t cfg5;
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uint32_t cfg6;
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uint32_t cfg7;
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uint32_t cfgdata_rtn;
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uint32_t cfgdata_out;
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uint32_t cfgctrl;
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uint32_t cfgstat;
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uint32_t dll;
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uint32_t aid;
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uint32_t id;
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uint32_t num_oscclk;
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uint32_t *oscclk;
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uint32_t *oscclk_reset;
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uint32_t cfg0_reset;
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qemu_irq remap;
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};
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#endif
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